Visible to Intel only — GUID: wyu1474669651641
Ixiasoft
2.1. Step 1: Create Simple Flip-Flop Design
2.2. Step 2: Define I/O Delay Chain and Clock Settings
2.3. Step 3: Specify Device Operating Conditions
2.4. Step 4: View IOE Timing Delay with Report Path
2.5. Scripted IOE Information Generation
2.6. Document Revision History for AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs
Visible to Intel only — GUID: wyu1474669651641
Ixiasoft
1.2. Step 2: Define I/O Standard and Pin Locations
The specific pin locations and I/O standard you assign to the device pins impacts the timing parameter values. Follow these steps to assign the pin I/O standard and location constraints:
- Click Assignments > Pin Planner.
- Assign pin location and I/O standard constraints according to your design specifications. Enter the Node Name, Direction, Location, and I/O Standard values for the pins in the design in the All Pins spreadsheet. Alternatively, drag node names into the Pin Planner package view.
Figure 4. Pin Locations and I/O Standards Assignments in Pin Planner
- To compile the design, click Processing > Start Compilation. The Compiler generates I/O timing information during full compilation, and automatically launches the Timing Analyzer with updated netlist at the end of full compilation.