Visible to Intel only — GUID: vvf1638309169558
Ixiasoft
2.1. Step 1: Create Simple Flip-Flop Design
2.2. Step 2: Define I/O Delay Chain and Clock Settings
2.3. Step 3: Specify Device Operating Conditions
2.4. Step 4: View IOE Timing Delay with Report Path
2.5. Scripted IOE Information Generation
2.6. Document Revision History for AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Intel FPGAs
Visible to Intel only — GUID: vvf1638309169558
Ixiasoft
2.2. Step 2: Define I/O Delay Chain and Clock Settings
The I/O delay chain setting that you specify determines the minimum and maximum delay path from input pin to output pin through each register. specifies the range of I/O delay chain settings for this example.
Setting | Maximum Value | Minimum Value |
---|---|---|
Input Delay Chain | 63 | 0 |
Output Delay Chain | 15 | 0 |
To assign the I/O delay chain settings, follow these steps:
- Click Assignments > Assignment Editor.
- In the Assignment Editor, assign settings to registers and pins, according to your design specifications, as the following example assignments show:
Figure 13. Registers and Pins in Assignment Editor
- To compile the design, click Processing > Start Compilation. The Compiler implements the assignments during compilation, and then launches the Timing Analyzer automatically.