Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Stratix® 10 Devices

ID 683100
Date 8/05/2024
Public
Document Table of Contents

1.5. Release Information

IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme. If an IP core version is not listed, the user guide for the previous IP core version applies.
The IP versioning scheme (X.Y.Z) number changes from one software version to another. A change in:
  • X indicates a major revision of the IP. If you update your Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 6.   Low Latency 100G Ethernet Intel FPGA IP Current Release Information

Item

Description

Version

19.2.0

Release Date

2020.04.13

Ordering Codes

Low Latency 100G Ethernet MAC and PHY: IP-100GEUMACPHY

Low Latency 100G Ethernet KR/CR Variant: IP-ETH-100GEUKRCR