Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Stratix® 10 Devices

ID 683100
Date 8/05/2024
Public
Document Table of Contents

1.3. IP Core Verification

To ensure functional correctness of the Low Latency 100G Ethernet Intel FPGA IP core, Intel performs extensive validation through both simulation and hardware testing. Before releasing a version of the Low Latency 100G Ethernet Intel FPGA IP core, Intel runs comprehensive regression tests in the current or associated version of the Quartus® Prime software.

Intel verifies that the current version of the Quartus® Prime software compiles the previous version of each IP core. Any exceptions to this verification are reported in the Intel FPGA IP Release Notes. Intel does not verify compilation with IP core versions older than the previous release.