Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Stratix® 10 Devices

ID 683100
Date 8/05/2024
Public
Document Table of Contents

6.8. Clocks

You must set the transceiver reference clock (clk_ref) frequency to a value that the IP core supports. The Low Latency 100G Ethernet Intel FPGA IP core supports a clk_ref frequency of 644.53125 MHz or 322.265625 MHz ±100 ppm. The ±100ppm value is required for any clock source providing the transceiver reference clock.

Table 19.  Clock InputsDescribes the input clocks that you must provide.

Signal Name

Description

clk_ref

The input clock clk_ref is the reference clock for the transceiver RX CDR PLL and the RS-FEC PLLs.

This clock must have a frequency of 644.53125 MHz with a ±100 ppm accuracy per the IEEE 802.3ba-2010 Ethernet Standard.

In addition, clk_ref must meet the jitter specification of the IEEE 802.3ba-2010 Ethernet Standard.

The PLL and clock generation logic use this reference clock to derive the transceiver and PCS clocks. The input clock should be a high quality signal on the appropriate dedicated clock pin. Refer to the relevant device datasheet for transceiver reference clock phase noise specifications.

tx_serial_clk[1:0]

These two input clocks are part of the external PLL interface. The IP core fans out each clock to target two of the four transceiver PHY links. You must drive these clocks from two ATX PLLs that you configure separately from the Low Latency 100G Ethernet Intel FPGA IP core. The required frequency is 12.890625 GHz.

clk_status

Clocks the control and status interface. clk_status is expected to be a 100–162 MHz clock. If AN/LT option is enabled, the clk_status and reconfig_clk must be connected to the same clock.

reconfig_clk

Clocks the transceiver reconfiguration interface. reconfig_clk is expected to be a 100–162 MHz clock. If AN/LT option is enabled, the clk_status and reconfig_clk must be connected to the same clock.

Table 20.  Clock OutputsDescribes the output clocks that the IP core provides. In most cases these clocks participate in internal clocking of the IP core as well.

Signal Name

Description

clk_txmac

The TX clock for the IP core is clk_txmac. The TX MAC clock frequency is 390.625  MHz.

This clock is guaranteed stable when tx_lanes_stable is high.

clk_rxmac

The RX clock for the IP core is clk_rxmac. The RX MAC clock frequency is 390.625  MHz.

This clock is only reliable when rx_pcs_ready has the value of 1. The IP core generates clk_rxmac from a recovered clock that relies on the presence of incoming RX data.