Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Stratix® 10 Devices

ID 683100
Date 8/05/2024
Public
Document Table of Contents

4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath

The Low Latency 100G Ethernet Intel FPGA IP RX MAC receives Ethernet frames from the PHY and forwards the payload with relevant header bytes to the client after performing some MAC functions on header bytes.

Figure 8. Flow of Frame Through the MAC RX Without Preamble Pass-Through Illustrates the typical flow of frame through the MAC RX when the preamble pass-through feature is turned off. In this figure, <p> is payload size, and <s> is the number of pad bytes (0–46 bytes).
Figure 9. Flow of Frame Through the MAC RX With Preamble Pass-Through Turned On Illustrates the typical flow of frame through the MAC RX when the preamble pass-through feature is turned on. In this figure, <p> is payload size, and <s> is the number of pad bytes (0–46 bytes).

The following sections describe the functions performed by the RX MAC: