Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Stratix® 10 Devices

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ID 683100
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
1. Low Latency 100G Ethernet Intel FPGA IP Overview 2. Getting Started 3. IP Core Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Registers 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives 11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide
1. Low Latency 100G Ethernet Intel FPGA IP Overview x
1.1. Low Latency 100G Ethernet Intel FPGA IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. Low Latency 100G Ethernet Intel FPGA IP Core Device Family Support 1.2.2. Low Latency 100G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. IP Core Testbenches 2.7. Compiling the Full Design and Programming the FPGA
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLLs 2.5.3. Placement Settings for the Low Latency 100G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. High Level System Overview 4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath 4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath 4.4. Flow Control 4.5. User Interface to Ethernet Transmission 4.6. Auto Negotiation and Link Training 4.7. Auto Adaptation
4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath x
4.2.1. Preamble, Start, and SFD Insertion 4.2.2. Length/Type Field Processing 4.2.3. Frame Padding 4.2.4. Frame Check Sequence (CRC-32) Insertion 4.2.5. Inter-Packet Gap Adjustment 4.2.6. Error Insertion Test and Debug Feature 4.2.7. TX PCS 4.2.8. TX RSFEC
4.3. Low Latency 100G Ethernet Intel FPGA IP Core RX Datapath x
4.3.1. Low Latency 100G Ethernet Intel FPGA IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. Low Latency 100G Ethernet Intel FPGA IP Core FCS (CRC-32) Removal 4.3.4. Low Latency 100G Ethernet Intel FPGA IP Core CRC Checking 4.3.5. Low Latency 100G Ethernet Intel FPGA IP Core Malformed Packet Handling 4.3.6. RX CRC Forwarding 4.3.7. Inter-Packet Gap 4.3.8. RX PCS 4.3.9. RX RSFEC
4.4. Flow Control x
4.4.1. TX Pause/PFC Flow Control Transmission 4.4.2. XON/XOFF Pause Frames
4.5. User Interface to Ethernet Transmission x
4.5.1. Order of Transmission 4.5.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon-MM Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
6.4. Transceiver Reconfiguration Signals x
6.4.1. Disabling Background Calibration
7. Registers x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. TX Reed-Solomon FEC Registers 7.7. RX Reed-Solomon FEC Registers 7.8. Auto-Negotiation and Link Training Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
7.8. Auto-Negotiation and Link Training Registers x
7.8.1. AN/LT Sequencer Config 7.8.2. AN/LT Sequencer Status 7.8.3. Auto Negotiation Config Register 1 7.8.4. Auto Negotiation Config Register 2 7.8.5. Auto Negotiation Status Register 7.8.6. Auto Negotiation Config Register 3 7.8.7. Auto Negotiation Config Register 4 7.8.8. Auto Negotiation Config Register 5 7.8.9. Auto Negotiation Config Register 6 7.8.10. Auto Negotiation Status Register 1 7.8.11. Auto Negotiation Status Register 2 7.8.12. Auto Negotiation Status Register 3 7.8.13. Auto Negotiation Status Register 4 7.8.14. Auto Negotiation Status Register 5 7.8.15. Link Training Config Register 1 7.8.16. Link Training Config Register 2 7.8.17. Link Training Status Register 1 7.8.18. Link Training Config Register for Lane 0 7.8.19. Link Training Frame Contents for Lane 0 7.8.20. Local Transceiver TX EQ 1 Settings for Lane 0 7.8.21. Local Transceiver TX EQ 2 Settings for Lane 0 7.8.22. Local Link Training Parameters 7.8.23. Link Training Config Register for Lane 1 7.8.24. Link Training Frame Contents for Lane 1 7.8.25. Local Transceiver TX EQ 1 Settings for Lane 1 7.8.26. Local Transceiver TX EQ 2 Settings for Lane 1 7.8.27. Link Training Config Register for Lane 2 7.8.28. Link Training Frame Contents for Lane 2 7.8.29. Local Transceiver TX EQ 1 Settings for Lane 2 7.8.30. Local Transceiver TX EQ 2 Settings for Lane 2 7.8.31. Link Training Config Register for Lane 3 7.8.32. Link Training Frame Contents for Lane 3 7.8.33. Local Transceiver TX EQ 1 Settings for Lane 3 7.8.34. Local Transceiver TX EQ 2 Settings for Lane 3
9. Ethernet Toolkit Overview x
9.1. Features
1. Low Latency 100G Ethernet Intel FPGA IP Overview
2. Getting Started
3. IP Core Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Registers
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 100G Ethernet Intel FPGA IP Core User Guide Archives
11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide

11. Document Revision History for the Low Latency 100G Ethernet Intel FPGA IP Core User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.08.05 24.2 22.2.0 Updated instructions for ModelSim* SE or QuestaSim* or Questa* Intel® FPGA Edition in IP Core Generated Files table.
2022.02.16 21.1 19.2.0 Added "Low Latency 100G Ethernet KR/CR Variant: IP-ETH-100GEUKRCR" to Ordering Codes to enable KR/CR (AN/LT)
2021.05.21 21.1 19.2.0 Removed support for the Intel Agilex™ device family.
2020.09.28 20.3 — Made the following changes:
  • Revised title from Low Latency 100G Ethernet Stratix® 10 FPGA IP Core User Guide to Low Latency 100G Ethernet Intel FPGA IP Core User Guide: For Stratix® 10 and Agilex™ 7 Devices. The user guide supports Stratix® 10 and Agilex™ 7 devices.
  • Added support for Agilex™ 7 devices.
  • Updated Performance and Resource Utilization section:
    • Updated resource utilization for Stratix® 10 devices in the IP Core FPGA Resource Utilization for Stratix® 10 Devices table.
    • Added resource utilization for Agilex™ 7 devices in the IP Core FPGA Resource Utilization for Agilex™ 7 Devices table.
  • Updated the Low Latency 100G Ethernet Intel FPGA IP Signals and Interfaces figure.
  • Removed flow control signals from the TX/RX MAC Interface to User Logic sections. Created a new Flow Control Interface topic to include pause_isert_tx0/tx1 and pause_insert_rx signals.
  • Corrected the width of the reconfiguration address from reconfig_address[13:0] to reconfig_address[12:0].
  • Revised figure displaying the traffic on the TX Avalon® -ST client interface in the TX MAC Interface to User Logic section.
  • Added new sections:
    • Auto Adaptation
    • Ethernet Toolkit
2020.04.13 20.1 19.2.0 Made the following changes:
  • Updated information on PLL configuration in the Adding the Transceiver PLLs section. The TX transceiver PLLs are instantiated with two Stratix® 10 ATX PLL IP cores, one as the main ATX PLL and another as a clock buffer.
  • Added PMA registers word offset in the Low Latency 100G Ethernet Intel FPGA IP Core Register Map Overview table.
2020.03.16 19.4 19.1.1
  • Updated Stratix® 10 device family support status from Advance to Final in the Low Latency 100G Ethernet Intel FPGA IP Core Device Family Support table.
  • Removed the updated PLL configuration information in the Adding the Transceiver PLLs section.
  • Updated information on multichannel configuration in the Disabling Background Calibration section.
2019.12.16 19.4 19.1.1
  • Updated information on PLL configuration in the Adding the Transceiver PLLs section.
  • Added pause_insert_tx0 and pause_insert_tx1 signals in the Signals of the Avalon® streaming interfaceTX Client Interface table.
  • Added pause_receive_rx signal in the Signals of the Avalon® streaming interfaceRX Client Interface table.
  • Added a new topic: Disabling Background Calibration.
  • Updated description of RX PFC Enable in the RX Flow Control Registers table.
  • Removed KHZ_REF from PHY Registers table.
  • Updated description of EIO_RX_SOFT_PURGE_S[12] in the PHY Registers table.
2019.08.02 19.2 19.1.1
  • Replaced Altera Debug Master Endpoint (ADME) with Native PHY Debug Master Endpoint (NPDME).
  • Added ATX PLL reference clock clarification in the Adding the Transceiver PLLs section.
  • Updated EIO_RX_SOFT_PURGE_S signal in the Registers section.
  • Added IP versioning description in the Released Information section.
2018.09.24 18.1 —
  • Updated the IP core block diagram.
  • Added feature support for Auto-negotiation (AN) and Link training (LT).
  • Added new parameters for AN/LT Options.
  • Added a new section: Auto-Negotiation and Link Training.
  • Added registers under a new section: Auto-Negotiation and Link Training Registers.
  • Added register for dynamic control of RS-FEC block in the Table: PHY Registers.
2018.07.18 18.0 —
  • Added flow control, TX error insertion, and RX control frame indication features in supported features list.
  • Updated release information for the IP core.
  • Added 322.265625 MHz clock option to the PHY reference frequency parameter.
  • Added Enable MAC Flow Control, Number of queues in priority flow control, and Enable link fault generation parameters in the IP core parameter table.
  • Added PCS compliance table Functional Description section.
  • Added pause_insert_tx0, pause_insert_tx1, and pause_receive_rx signals in the Low Latency 100G Ethernet Intel FPGA Signals and Interfaces diagram.
  • Updated PHY_CONFIG and RX_FEC_STATUS registers' default value.
  • Added ERR_INJ, LINK_FAULT, Pause/PFC Flow Control registers in the Registers section.
  • Added Inter-Packet Gap Adjustment topic.
  • Updated the clk_status and reconfig_clk frequency to 100 - 162 MHz.
2017.11.06 17.1 — Initial public release.
Level Two Title