Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Stratix® 10 Devices

ID 683100
Date 8/05/2024
Public
Document Table of Contents

2.7. Compiling the Full Design and Programming the FPGA

You can use the Start Compilation command on the Processing menu in the Quartus® Prime Pro Edition software to compile your design. After successfully compiling your design, program the targeted Intel device with the Programmer and verify the design in hardware.

Note: The Low Latency 100G Ethernet Intel FPGA IP core design example synthesis directories include Synopsys Constraint (.sdc) files that you can copy and modify for your own design.