AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

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ID 683092
Date 4/03/2019
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Document Table of Contents
Document Table of Contents x
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs x
Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
MIPI D-PHY Specifications x
MIPI D-PHY Specifications for Receiver MIPI D-PHY Specifications for Transmitter
FPGA I/O Standard Specifications x
FPGA I/O Standard Specifications for MIPI Receiver FPGA I/O Standard Specifications for MIPI Transmitter
IBIS Simulation x
FPGA As Receiver: HS-RX and LP-RX Modes Simulation FPGA As Receiver: Simulation Results FPGA As Transmitter: HS-TX and LP-TX Modes Simulation FPGA As Transmitter: Simulation Results
FPGA As Receiver: Simulation Results x
FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Receiver: Simulation Results Using Cyclone® V Devices FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
FPGA As Transmitter: Simulation Results x
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Transmitter: Simulation Results Using Cyclone® V Devices FPGA As Transmitter: Simulation Results Using Intel® MAX® 10 Devices
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

MIPI D-PHY Specifications for Transmitter

Table 4.  High-Speed MIPI D-PHY Transmitter DC SpecificationsThis table shows the MIPI D-PHY transmitter high-speed signal DC specifications as stipulated in the MIPI D-PHY specifications from the MIPI Alliance.
Parameter Description Minimum Typical Maximum Unit
VCMTX High-speed transmit static common-mode voltage 4 150 200 250 mV
|ΔVCMTX(1,0)| VCMTX mismatch when output is Differential-1 or Differential-0 5 — — 5 mV
|VOD| High-speed transmit differential voltage 4 140 200 270 mV
|ΔVOD| VOD mismatch when output is Differential-1 or Differential-0 5 — — 10 mV
VOHHS High-speed output high voltage 4 — — 360 mV
ZOS Single-ended output impedance 40 50 62.5 Ω
ΔZOS Single-ended output impedance mismatch — — 10 %
Table 5.  Low-Power MIPI D-PHY Transmitter DC SpecificationsThis table shows the MIPI D-PHY transmitter low-power signal DC specifications as stipulated in the MIPI D-PHY specifications from the MIPI Alliance.
Parameter Description Minimum Typical Maximum Unit
VOH Thevenin output high level 1.1 1.2 1.3 V
VOL Thevenin output low level –50 — 50 mV
4 When driving into load impedance within the ZID range.
5 Recommended to minimize ΔVOD and ΔVCMTX(1,0) to minimize radiation and optimize signal integrity.
Level Two Title