AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

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ID 683092
Date 4/03/2019
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Document Table of Contents x
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs x
Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
MIPI D-PHY Specifications x
MIPI D-PHY Specifications for Receiver MIPI D-PHY Specifications for Transmitter
FPGA I/O Standard Specifications x
FPGA I/O Standard Specifications for MIPI Receiver FPGA I/O Standard Specifications for MIPI Transmitter
IBIS Simulation x
FPGA As Receiver: HS-RX and LP-RX Modes Simulation FPGA As Receiver: Simulation Results FPGA As Transmitter: HS-TX and LP-TX Modes Simulation FPGA As Transmitter: Simulation Results
FPGA As Receiver: Simulation Results x
FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Receiver: Simulation Results Using Cyclone® V Devices FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
FPGA As Transmitter: Simulation Results x
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Transmitter: Simulation Results Using Cyclone® V Devices FPGA As Transmitter: Simulation Results Using Intel® MAX® 10 Devices
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

MIPI D-PHY Specifications for Receiver

Table 2.  High-Speed MIPI D-PHY Receiver DC SpecificationsThis table shows the MIPI D-PHY receiver high-speed signal DC specifications as stipulated in the MIPI D-PHY specifications from the MIPI Alliance.
Parameter Description Minimum Typical Maximum Unit
VCMRX(DC) Common-mode voltage high-speed receive mode 70 — 330 mV
VIDTH Differential input high threshold — — 70 mV
VIDTL Differential input low threshold –70 — — mV
VIHHS Single-ended input high voltage — — 460 mV
VILHS Single-ended input low voltage –40 — — mV
VTERM-EN Single-ended threshold for high-speed termination enable — — 450 mV
ZID Differential input impedance 80 100 125 Ω
Table 3.  Low-Power MIPI D-PHY Receiver DC SpecificationsThis table shows the MIPI D-PHY receiver low-power signal DC specifications as stipulated in the MIPI D-PHY specifications from the MIPI Alliance.
Parameter Description Minimum Typical Maximum Unit
VIH Logic 1 input voltage 880 — — mV
VIL Logic 0 input voltage, not in ultra low power (ULP) state — — 550 mV
Level Two Title