AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

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ID 683092
Date 4/03/2019
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Document Table of Contents x
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs x
Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
MIPI D-PHY Specifications x
MIPI D-PHY Specifications for Receiver MIPI D-PHY Specifications for Transmitter
FPGA I/O Standard Specifications x
FPGA I/O Standard Specifications for MIPI Receiver FPGA I/O Standard Specifications for MIPI Transmitter
IBIS Simulation x
FPGA As Receiver: HS-RX and LP-RX Modes Simulation FPGA As Receiver: Simulation Results FPGA As Transmitter: HS-TX and LP-TX Modes Simulation FPGA As Transmitter: Simulation Results
FPGA As Receiver: Simulation Results x
FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Receiver: Simulation Results Using Cyclone® V Devices FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
FPGA As Transmitter: Simulation Results x
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Transmitter: Simulation Results Using Cyclone® V Devices FPGA As Transmitter: Simulation Results Using Intel® MAX® 10 Devices
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

FPGA I/O Standard Specifications for MIPI Transmitter

The DC specifications for Differential HSTL-18, 1.8 V LVCMOS, and 2.5 V LVCMOS I/O standards are as stipulated in the device datasheets for the respective devices. When an FPGA functions as a MIPI D-PHY transmitter, the transmitted high-speed and low-power signals from the FPGA I/O are expected to meet the high-speed and low-power MIPI D-PHY receiver specifications with passive resistor network.

Table 10.  Differential HSTL-18, 1.8 V LVCMOS, and 2.5 V LVCMOS I/O Standards DC Specifications
I/O Standard VCCIO (V) VOL (V) VOH (V)
Min Typ Max Max Min
HSTL-188 Class I, II 1.71 1.8 1.89 0.4 VCCIO – 0.4
1.8 V LVCMOS 1.71 1.8 1.89 0.45 VCCIO – 0.45
2.5 V LVCMOS 2.375 2.5 2.625 0.4 2
Related Information
8 Differential HSTL-18 is a pseudo differential I/O standard consists of two single-ended HSTL-18 output buffers. One single-ended output buffer is the P channel and another single-ended output buffer is the N channel (inversion of P channel). The output differential signal (VOD) is the difference of VOH–VOL. The output common mode voltage (VOCM) is the signal crossing point for P and N channels.
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