AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

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ID 683092
Date 4/03/2019
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Document Table of Contents x
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs x
Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
MIPI D-PHY Specifications x
MIPI D-PHY Specifications for Receiver MIPI D-PHY Specifications for Transmitter
FPGA I/O Standard Specifications x
FPGA I/O Standard Specifications for MIPI Receiver FPGA I/O Standard Specifications for MIPI Transmitter
IBIS Simulation x
FPGA As Receiver: HS-RX and LP-RX Modes Simulation FPGA As Receiver: Simulation Results FPGA As Transmitter: HS-TX and LP-TX Modes Simulation FPGA As Transmitter: Simulation Results
FPGA As Receiver: Simulation Results x
FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Receiver: Simulation Results Using Cyclone® V Devices FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
FPGA As Transmitter: Simulation Results x
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Transmitter: Simulation Results Using Cyclone® V Devices FPGA As Transmitter: Simulation Results Using Intel® MAX® 10 Devices
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

Conclusion

The passive resistor network in this application illustrates and validates the IBIS simulations. You can use the passive resistor network to build a FPGA I/O based compatible MIPI D-PHY for receiving or transmitting both high-speed and low-power signals using various FPGA GPIO connected. The passive resistor network is capable to enable an electrically compatible connection between Intel FPGA I/O to a MIPI D-PHY TX or RX device via MIPI D-PHY interface.

Table 11.  Passive Resistor Values Used in the IBIS SimulationsRefer to the FPGA Unidirectional Receiver Implementation Block Diagram and FPGA Unidirectional Transmitter Implementation Block Diagram for the simulation block diagrams.
FPGA Implementation Passive Resistor Value (Ω)
Rx Ry xx yy zz
FPGA unidirectional receiver implementation 300 100 — — —
FPGA unidirectional transmitter implementation — — 150 60 100
Table 12.  Maximum Achievable Data Rate Using Intel FPGA GPIOThe maximum achievable data rate depends on the device speed grade.
Device Supported Data Rate (Mbps)
Cyclone® IV, Cyclone® V, Intel® Cyclone® 10 LP 840
Intel® MAX® 10 720

Intel recommends performing HSPICE/IBIS simulations to verify the signal quality based on your specific system setup and PCB info at the desired operating frequency.

Actual achievable frequency depends on design- and system-specific factors. Perform HSPICE/IBIS simulation based on your specific design, system setup, and PCB info to determine the maximum achievable frequency.

The MIPI D-PHY passive solution with different approaches (I/O, passive network, and FPGA devices) are validated using multiple demo boards. You can use the following demo boards as reference:

  • Intel 10M50 Evaluation Kit, EK-10M50F484 (available March 2016 onwards)
  • Arrow DECA Intel® MAX® 10 Evaluation Kit

For more information about the demo boards, contact your local Intel sales representatives.

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