AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

Download PDF
ID 683092
Date 4/03/2019
Public
Document Table of Contents
Document Table of Contents x
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs x
Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
MIPI D-PHY Specifications x
MIPI D-PHY Specifications for Receiver MIPI D-PHY Specifications for Transmitter
FPGA I/O Standard Specifications x
FPGA I/O Standard Specifications for MIPI Receiver FPGA I/O Standard Specifications for MIPI Transmitter
IBIS Simulation x
FPGA As Receiver: HS-RX and LP-RX Modes Simulation FPGA As Receiver: Simulation Results FPGA As Transmitter: HS-TX and LP-TX Modes Simulation FPGA As Transmitter: Simulation Results
FPGA As Receiver: Simulation Results x
FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Receiver: Simulation Results Using Cyclone® V Devices FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
FPGA As Transmitter: Simulation Results x
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Transmitter: Simulation Results Using Cyclone® V Devices FPGA As Transmitter: Simulation Results Using Intel® MAX® 10 Devices
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices

Figure 4. HS-RX Mode Eye Diagram Measured At Cyclone® IV and Intel® Cyclone® 10 LP FPGA Receiver Die At 840 MbpsTrue (P) and Inverted (N) signals are plotted in purple and green. The P and N signals are overlapped. Differential signal (P-N) is plotted in yellow.
Figure 5. LP-RX Mode Waveform Measured At Cyclone® IV and Intel® Cyclone® 10 LP FPGA Receiver Die for LP11 and LP00 States at 10 MbpsDP signal is shown in blue and DN signal is shown in pink. The DN signal (pink) overlaps with the DP signal (blue) because both signals are driven on the same state (LP11, LP00).
Figure 6. LP-RX Mode Waveform Measured At Cyclone® IV and Intel® Cyclone® 10 LP FPGA Receiver Die for LP10 and LP01 States at 10 MbpsBoth DP and DN signals are not overlapped because they are driven out of phase (LP10, LP01).
Level Two Title