PHY Lite for Parallel Interfaces Intel® FPGA IP Cores Release Notes

ID 683090
Date 4/01/2024
Public
Document Table of Contents

PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v5.0.0

Table 1.  v5.0.0 2024.04.01
Quartus® Prime Version Description Impact
24.1
  • Changed the default value of the GROUP_X_RCVEN_TO_READ_VALID_OFFSET parameter in Agilex™ 7.
  • Internally connected reset to permit_cal port of the IOPLL.
Intel requires that you regenerate your IP.