PHY Lite for Parallel Interfaces Intel® FPGA IP Cores Release Notes

ID 683090
Date 4/01/2024
Public
Document Table of Contents

Altera PHYLite for Memory IP Core v14.1

Table 17.  v14.1 December 2014
Description Impact
Added internal PLL additional clock export parameter -
Added setup delay constraint timing parameters in the Group tabs in the parameter editor -