PHY Lite for Parallel Interfaces Intel® FPGA IP Cores Release Notes

ID 683090
Date 4/01/2024
Public
Document Table of Contents

Altera PHYLite for Parallel Interfaces IP Core v16.0

Table 15.  v16.0 May 2016
Description Impact
Added parameter, VCO clock frequency, to inform users on the internally calculated VCO clock.
Changed of IP maximum supported frequency per device speed grade.
Added issp.tcl file in Dynamic Reconfiguration with Debug Kit Design Example to enable users to reset the system and probe internal signals.