PHY Lite for Parallel Interfaces Intel® FPGA IP Cores Release Notes

ID 683090
Date 4/01/2024
Public
Document Table of Contents

Altera PHYLite for Parallel Interfaces IP Core v15.1

Table 16.  v15.1 November 2015
Description Impact
Added new debug kit example design using Nios II for dynamic reconfigurations. -
Added parameter, Copy parameters from another group, to allow copying parameters from one DQ group to another DQ group. -
Added new parameters group, Group <x> Dynamic Reconfiguration Timing Settings, for users to select dynamic reconfiguration algorithm for timing analysis. -
Added parameter, OCT enable size, for users to specify the interpolator clock cycle delay required to ensure OCT is turned on before sampling any input data. -
Added parameters, Inter Symbol Interference of the Read Channel and Inter Symbol Interference of the Write Channel, for users to specify the Inter Symbol Interference values for read and write channels for timing analysis. -