PHY Lite for Parallel Interfaces Intel® FPGA IP Cores Release Notes

ID 683090
Date 4/01/2024
Public
Document Table of Contents

Altera PHYLite for Memory IP Core v14.0 Arria 10 Edition

Table 18.  v14.0 Arria 10 Edition August 2014
Description Impact
Added dynamic reconfiguration -
Added I/O standard and OCT settings -
Added complementary strobe type -
Changed pll_locked port name to interface_locked -