PHY Lite for Parallel Interfaces Intel® FPGA IP Cores Release Notes

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ID 683090
Date 4/01/2024
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PHY Lite for Parallel Interfaces Intel® FPGA IP Cores Release Notes
PHY Lite for Parallel Interfaces Intel® FPGA IP Cores Release Notes x
PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) Release Notes ( Agilex™ 7 M-Series Devices) PHY Lite for Parallel Interfaces Intel® FPGA IP (altera_phylite_s20) Release Notes ( Agilex™ 7 F-Series and I-Series Devices) PHY Lite for Parallel Interfaces Intel FPGA IP Core v19.3.0 PHY Lite for Parallel Interfaces Intel FPGA IP Core v18.1 PHY Lite for Parallel Interfaces Intel FPGA IP Core v18.0 Intel FPGA PHYLite for Parallel Interfaces IP Core v17.1 Altera PHYLite for Parallel Interfaces IP Core v16.0 Altera PHYLite for Parallel Interfaces IP Core v15.1 Altera PHYLite for Memory IP Core v14.1 Altera PHYLite for Memory IP Core v14.0 Arria 10 Edition PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) Release Notes ( Agilex™ 7 M-Series Devices) x
PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v5.0.0 PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v4.1.0 PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v4.0.0 PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v3.0.0 PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v2.0.0
PHY Lite for Parallel Interfaces Intel® FPGA IP (altera_phylite_s20) Release Notes ( Agilex™ 7 F-Series and I-Series Devices) x
PHY Lite for Parallel Interfaces Intel Agilex FPGA IP (altera_phylite_s20) v22.3.0 PHY Lite for Parallel Interfaces Intel Agilex FPGA IP (altera_phylite_s20) v22.1.0 PHY Lite for Parallel Interfaces Intel Agilex FPGA IP (altera_phylite_s20) v21.0.0 PHY Lite for Parallel Interfaces Intel Agilex FPGA IP (altera_phylite_s20) v20.3.0
PHY Lite for Parallel Interfaces Intel® FPGA IP Cores Release Notes

PHY Lite for Parallel Interfaces Intel Agilex FPGA IP v20.3.0

Table 3.  v20.3.0 2020.12.14
Intel® Quartus® Prime Version Description Impact
20.4
  • Added support for dynamic reconfiguration.
  • Added design example with dynamic reconfiguration.
  • Added Pin Placement tab in the parameter editor, to allow pin placement settings for all groups and graphical support of data/strobe pin placement within sub-bank. Removed pin placement settings in each group.
  • Added support for half-rate and full-rate.
  • Added support for I/O sub-bank pin 7 in each lane to be used as data pin.
  • Added sub-bank ID to facilitate pin placement at the IP generation stage.
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Level Two Title