Intel® Acceleration Stack User Guide: Intel FPGA Programmable Acceleration Card N3000

Download PDF
ID 683040
Date 6/14/2021
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. System Requirements 3. Hardware Installation 4. Installing the OPAE Software 5. OPAE Tools 6. Sample Test: Native Loopback 7. Installing the Intel XL710 Driver 8. Configuring Ethernet Interfaces 9. Testing Network Loopback Using Data Plane Development Kit (DPDK) 10. Graceful Shutdown 11. Single Event Upset (SEU) 12. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000 A. Troubleshooting B. Upgrade your Intel® FPGA PAC N3000 with Production Version of BMC and Intel® Arria® 10 Image C. Configure the 4.19 Kernel D. fpgabist Sample Output
1. About this Document x
1.1. Acronym List
2. System Requirements x
2.1. Cooling Requirements
3. Hardware Installation x
3.1. Installing the Intel® FPGA PAC N3000
4. Installing the OPAE Software x
4.1. Install Additional Packages 4.2. Install the Release Package 4.3. Identify the Intel® MAX® 10 Version on your Intel® FPGA PAC N3000
4.2. Install the Release Package x
4.2.1. Remove Previous OPAE Packages 4.2.2. Install the Acceleration Stack for Runtime 4.2.3. Install the Acceleration Stack for Development 4.2.4. Verify the OPAE Installation 4.2.5. Install the Configuration Files
4.3. Identify the Intel® MAX® 10 Version on your Intel® FPGA PAC N3000 x
4.3.1. FPGA Factory Image Overview
5. OPAE Tools x
5.1. Using fpgasupdate 5.2. Using fpgainfo 5.3. Test PCIe and External Memories with fpgabist 5.4. Test Network Loopback using fpgadiag
7. Installing the Intel XL710 Driver x
7.1. Updating the Intel XL710 Firmware
8. Configuring Ethernet Interfaces x
8.1. Modifying the Interface Maximum Transmission Unit (MTU) Size 8.2. Setting Forward Error Correction (FEC) Mode 8.3. Ethernet Pause Flow Control 8.4. Get Link Status and Statistics
9. Testing Network Loopback Using Data Plane Development Kit (DPDK) x
9.1. Test Using an External Traffic Generator 9.2. Test Using a Packet Generator 9.3. Troubleshooting in DPDK 9.4. Revert Back from DPDK to OPAE
10. Graceful Shutdown x
10.1. Background 10.2. Using OPAE 10.3. Using DPDK
11. Single Event Upset (SEU) x
11.1. OPAE Handling of SEU 11.2. DPDK Handling of SEU
A. Troubleshooting x
A.1. If OPAE installation verification fails, how to install OPAE manually?
B. Upgrade your Intel® FPGA PAC N3000 with Production Version of BMC and Intel® Arria® 10 Image x
B.1. Upgrading from 1.1 Beta to Production Version B.2. Upgrading from 1.1 Alpha-2 or Older to Production Version
B.1. Upgrading from 1.1 Beta to Production Version x
B.1.1. Root Entry Hash Programmed B.1.2. Root Entry Hash Not Programmed
D. fpgabist Sample Output x
D.1. For 2x2x25G Configuration D.2. For 8x10G Configuration
1. About this Document
2. System Requirements
3. Hardware Installation
4. Installing the OPAE Software
5. OPAE Tools
6. Sample Test: Native Loopback
7. Installing the Intel XL710 Driver
8. Configuring Ethernet Interfaces
9. Testing Network Loopback Using Data Plane Development Kit (DPDK)
10. Graceful Shutdown
11. Single Event Upset (SEU)
12. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000
A. Troubleshooting
B. Upgrade your Intel® FPGA PAC N3000 with Production Version of BMC and Intel® Arria® 10 Image
C. Configure the 4.19 Kernel
D. fpgabist Sample Output

9.3. Troubleshooting in DPDK

If you see error as below while starting pktgen, follow the listed steps: 
Port  0: Link Up - speed 25000 Mbps - full-duplex <Enable promiscuous mode>
Port  1: Link Up - speed 25000 Mbps - full-duplex <Enable promiscuous mode>
 
RX processing lcore:   1 rx:  1 tx:  0
PANIC in pktgen_main_rx_loop():
*** port 0 socket ID 0 has different socket ID for lcore 1 socket ID 1
7:  [/lib64/libc.so.6(clone+0x6d) [0x7ff79c354ead]]
6: [/lib64/libpthread.so.0(+0x7dd5) [0x7ff79c62bdd5]]
5: [./app/x86_64-native-linuxapp-gcc/pktgen(eal_thread_loop+0x1d4) [0x583594]]
4: [./app/x86_64-native-linuxapp-gcc/pktgen(pktgen_launch_one_lcore+0xa7) [0x4a8997]]
3: [./app/x86_64-native-linuxapp-gcc/pktgen() [0x4a1b1f]]
2: [./app/x86_64-native-linuxapp-gcc/pktgen(__rte_panic+0xb8) [0x46b941]]
1: [./app/x86_64-native-linuxapp-gcc/pktgen(rte_dump_stack+0x1a) [0x58935a]]
        Aborted (core dumped)
  1. Find the CPU (NUMA node/socket) connected to the Intel® FPGA PAC N3000.
    Figure 23. Example
  2. Run command to find the CPU to core mapping.
    $	RTE_SDK/usertools/cpu_layout.py
    Figure 24. Output
    This shows that all even cores [0, 2, 4, 6, 8, 10] are bound to socket 0 and all odd cores [1, 3, 5, 7, 9, 11] are bound to socket 1.
    Note: The NUMA node is same as the socket.
Since ports in this setup are bound to socket 0, even cores are used as lcores in the below command. Update the lcore in the command as per your system configuration. 
$  ./app/x86_64-native-linuxapp-gcc/pktgen -l 0,2,4 -n 4 --proc-type primary \
--log-level 7 --file-prefix pg -w 0000:16:00.0 -w 0000:16:00.1 -- \
-T -P -m 2.0 -m 4.1 -f themes/black-yellow.theme
Note: First core is always used by the management thread. lcore 2 is used to handle rx and tx for port 0. lcore 4 is used to handle rx and tx for port 1.
Level Two Title