Intel® Acceleration Stack User Guide: Intel FPGA Programmable Acceleration Card N3000

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ID 683040
Date 6/14/2021
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. System Requirements 3. Hardware Installation 4. Installing the OPAE Software 5. OPAE Tools 6. Sample Test: Native Loopback 7. Installing the Intel XL710 Driver 8. Configuring Ethernet Interfaces 9. Testing Network Loopback Using Data Plane Development Kit (DPDK) 10. Graceful Shutdown 11. Single Event Upset (SEU) 12. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000 A. Troubleshooting B. Upgrade your Intel® FPGA PAC N3000 with Production Version of BMC and Intel® Arria® 10 Image C. Configure the 4.19 Kernel D. fpgabist Sample Output
1. About this Document x
1.1. Acronym List
2. System Requirements x
2.1. Cooling Requirements
3. Hardware Installation x
3.1. Installing the Intel® FPGA PAC N3000
4. Installing the OPAE Software x
4.1. Install Additional Packages 4.2. Install the Release Package 4.3. Identify the Intel® MAX® 10 Version on your Intel® FPGA PAC N3000
4.2. Install the Release Package x
4.2.1. Remove Previous OPAE Packages 4.2.2. Install the Acceleration Stack for Runtime 4.2.3. Install the Acceleration Stack for Development 4.2.4. Verify the OPAE Installation 4.2.5. Install the Configuration Files
4.3. Identify the Intel® MAX® 10 Version on your Intel® FPGA PAC N3000 x
4.3.1. FPGA Factory Image Overview
5. OPAE Tools x
5.1. Using fpgasupdate 5.2. Using fpgainfo 5.3. Test PCIe and External Memories with fpgabist 5.4. Test Network Loopback using fpgadiag
7. Installing the Intel XL710 Driver x
7.1. Updating the Intel XL710 Firmware
8. Configuring Ethernet Interfaces x
8.1. Modifying the Interface Maximum Transmission Unit (MTU) Size 8.2. Setting Forward Error Correction (FEC) Mode 8.3. Ethernet Pause Flow Control 8.4. Get Link Status and Statistics
9. Testing Network Loopback Using Data Plane Development Kit (DPDK) x
9.1. Test Using an External Traffic Generator 9.2. Test Using a Packet Generator 9.3. Troubleshooting in DPDK 9.4. Revert Back from DPDK to OPAE
10. Graceful Shutdown x
10.1. Background 10.2. Using OPAE 10.3. Using DPDK
11. Single Event Upset (SEU) x
11.1. OPAE Handling of SEU 11.2. DPDK Handling of SEU
A. Troubleshooting x
A.1. If OPAE installation verification fails, how to install OPAE manually?
B. Upgrade your Intel® FPGA PAC N3000 with Production Version of BMC and Intel® Arria® 10 Image x
B.1. Upgrading from 1.1 Beta to Production Version B.2. Upgrading from 1.1 Alpha-2 or Older to Production Version
B.1. Upgrading from 1.1 Beta to Production Version x
B.1.1. Root Entry Hash Programmed B.1.2. Root Entry Hash Not Programmed
D. fpgabist Sample Output x
D.1. For 2x2x25G Configuration D.2. For 8x10G Configuration
1. About this Document
2. System Requirements
3. Hardware Installation
4. Installing the OPAE Software
5. OPAE Tools
6. Sample Test: Native Loopback
7. Installing the Intel XL710 Driver
8. Configuring Ethernet Interfaces
9. Testing Network Loopback Using Data Plane Development Kit (DPDK)
10. Graceful Shutdown
11. Single Event Upset (SEU)
12. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000
A. Troubleshooting
B. Upgrade your Intel® FPGA PAC N3000 with Production Version of BMC and Intel® Arria® 10 Image
C. Configure the 4.19 Kernel
D. fpgabist Sample Output

10.1. Background

The Intel® FPGA PAC N3000 provides protective circuitry that automatically shuts down key board power supplies in the event of critical board sensors surpassing the fatal thresholds. The critical board sensors are listed below:
Table 14.  Critical Sensors
Sensor ID Sensor Upper Fatal Threshold Upper Warning Threshold Lower Fatal Threshold Lower Warning Threshold
12 FPGA Core Temperature 100°C 90°C X X
13 Board Temperature 85°C 75°C X X
25 12V Aux Voltage X X 10.56 V 11.40 V
3 12 V Backplane Voltage X X 10.56 V 11.40 V

For more information about sensors, refer to the Intel FPGA Programmable Acceleration Card N3000 Board Management Controller User Guide.

Surpassing the fatal thresholds of the above four critical sensors causes the Intel FPGA PAC PCIe buses to shut off, which could lead to a server Fatal PCIe Surprise Link Down event.

Intel provides two methods to prevent the server Fatal PCIe Surprise Link Down event. These methods mask PCIe Advanced Error Reporting (AER) registers for the Intel® FPGA PAC N3000 to avoid Surprise Link Down. If you are using DPDK and have unbound the OPAE FPGA driver, follow the method described under Using DPDK.

Note: Once the Intel® FPGA PAC N3000 surpasses the fatal threshold of a critical sensor, a server power cycle is required to recover operation of the Intel® FPGA PAC N3000.
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