Intel® Acceleration Stack User Guide: Intel FPGA Programmable Acceleration Card N3000

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ID 683040
Date 6/14/2021
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. System Requirements 3. Hardware Installation 4. Installing the OPAE Software 5. OPAE Tools 6. Sample Test: Native Loopback 7. Installing the Intel XL710 Driver 8. Configuring Ethernet Interfaces 9. Testing Network Loopback Using Data Plane Development Kit (DPDK) 10. Graceful Shutdown 11. Single Event Upset (SEU) 12. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000 A. Troubleshooting B. Upgrade your Intel® FPGA PAC N3000 with Production Version of BMC and Intel® Arria® 10 Image C. Configure the 4.19 Kernel D. fpgabist Sample Output
1. About this Document x
1.1. Acronym List
2. System Requirements x
2.1. Cooling Requirements
3. Hardware Installation x
3.1. Installing the Intel® FPGA PAC N3000
4. Installing the OPAE Software x
4.1. Install Additional Packages 4.2. Install the Release Package 4.3. Identify the Intel® MAX® 10 Version on your Intel® FPGA PAC N3000
4.2. Install the Release Package x
4.2.1. Remove Previous OPAE Packages 4.2.2. Install the Acceleration Stack for Runtime 4.2.3. Install the Acceleration Stack for Development 4.2.4. Verify the OPAE Installation 4.2.5. Install the Configuration Files
4.3. Identify the Intel® MAX® 10 Version on your Intel® FPGA PAC N3000 x
4.3.1. FPGA Factory Image Overview
5. OPAE Tools x
5.1. Using fpgasupdate 5.2. Using fpgainfo 5.3. Test PCIe and External Memories with fpgabist 5.4. Test Network Loopback using fpgadiag
7. Installing the Intel XL710 Driver x
7.1. Updating the Intel XL710 Firmware
8. Configuring Ethernet Interfaces x
8.1. Modifying the Interface Maximum Transmission Unit (MTU) Size 8.2. Setting Forward Error Correction (FEC) Mode 8.3. Ethernet Pause Flow Control 8.4. Get Link Status and Statistics
9. Testing Network Loopback Using Data Plane Development Kit (DPDK) x
9.1. Test Using an External Traffic Generator 9.2. Test Using a Packet Generator 9.3. Troubleshooting in DPDK 9.4. Revert Back from DPDK to OPAE
10. Graceful Shutdown x
10.1. Background 10.2. Using OPAE 10.3. Using DPDK
11. Single Event Upset (SEU) x
11.1. OPAE Handling of SEU 11.2. DPDK Handling of SEU
A. Troubleshooting x
A.1. If OPAE installation verification fails, how to install OPAE manually?
B. Upgrade your Intel® FPGA PAC N3000 with Production Version of BMC and Intel® Arria® 10 Image x
B.1. Upgrading from 1.1 Beta to Production Version B.2. Upgrading from 1.1 Alpha-2 or Older to Production Version
B.1. Upgrading from 1.1 Beta to Production Version x
B.1.1. Root Entry Hash Programmed B.1.2. Root Entry Hash Not Programmed
D. fpgabist Sample Output x
D.1. For 2x2x25G Configuration D.2. For 8x10G Configuration
1. About this Document
2. System Requirements
3. Hardware Installation
4. Installing the OPAE Software
5. OPAE Tools
6. Sample Test: Native Loopback
7. Installing the Intel XL710 Driver
8. Configuring Ethernet Interfaces
9. Testing Network Loopback Using Data Plane Development Kit (DPDK)
10. Graceful Shutdown
11. Single Event Upset (SEU)
12. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000
A. Troubleshooting
B. Upgrade your Intel® FPGA PAC N3000 with Production Version of BMC and Intel® Arria® 10 Image
C. Configure the 4.19 Kernel
D. fpgabist Sample Output

2.1. Cooling Requirements

The high performance devices installed on the Intel® FPGA PAC N3000 require server based forced air cooling to maintain proper operating temperature. This section provides air flow requirements for the Intel® FPGA PAC N3000. Sufficient airflow keeps the Intel® Arria® 10 GT junction temperature below 95 °C. Each data point corresponds to minimum airflow (Y-axis) through the card for a corresponding card inlet temperature (X-axis).

Figure 2. Air Flow Pattern
Key parameters:
  • Required Cooling Airflow (CFM): Volumetric flow rate, in cubic feet per minute, of air passing through the PCIe faceplate of the Intel® FPGA PAC N3000.
  • TJ FPGA Junction Temperature
  • TLA Local Ambient Temperature2: Temperature of forced air as it enters the Intel® FPGA PAC N3000.
    Note: In many systems, TLA is higher than the room ambient due to heating affects of chassis components.
Table 1.  Power and Thermal Requirements

The Intel® FPGA PAC N3000 uses a passive heatsink. The server must provide sufficient forced airflow to keep the FPGA within the following operating conditions:

Parameters Maximum Values
Intel® Arria® 10 FPGA Thermal Design Power (TDP)3 ≤ 69 W
Intel® FPGA PAC N3000 Thermal Design Power (TDP) ≤ 126 W
Recommended FPGA Maximum Operating Temperature 95°C
FPGA TJ-MAX or Thermal Protection Shutdown 100°C
Maximum TLA (forward airflow) 51°C
Maximum TLA (reverse airflow) 45°C
Figure 3. Forward Flow Cooling Curve
Table 2.  Local Air Inlet Temperature and Air Flow Values for Forward Cooling
To maintain TJ = 95°C

FPGA Power < 49 W

Board Power < 96 W

FPGA Power < 54 W

Board Power < 102 W

FPGA Power < 69 W

Board Power < 126 W (TDP)

Max. TLA (°C) Air Flow (CFM) Max. TLA (°C) Air Flow (CFM) Max. TLA (°C) Air Flow (CFM)
46 8 40.7 8 39.2 10
54.5 12 49.8 12 47.8 15
62 20 57.9 20 52.3 20
Figure 4. Reverse Flow Cooling Curve
Table 3.  Local Air Inlet Temperature and Air Flow Values for Reverse Cooling
To maintain TJ = 95°C

FPGA Power < 49 W

Board Power < 96 W

FPGA Power < 54 W

Board Power < 102 W

FPGA Power < 69 W

Board Power < 126 W (TDP)

Max. TLA (°C) Air Flow (CFM) Max. TLA (°C) Air Flow (CFM) Max. TLA (°C) Air Flow (CFM)
44.6 8 39.8 8 36.1 10
52.6 12 48 12 44.7 15
61 20 56 20 49.4 20
Note: These flow curves are based on numerical analysis and should be used as a starting point for thermal design estimation. Thermal performance of host systems may vary. Therefore, you should perform in-system thermal validation.
2 TLA values shown in the tables and charts of this section are informational, and may represent conditions outside of the supported operating range.
3

Intel® Arria® 10 FPGA TDP cannot be obtained from on-board BMC sensors. Use the Intel® Quartus® Prime Power Analyzer to verify compliance with this value for your design.

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