Intel® Acceleration Stack User Guide: Intel FPGA Programmable Acceleration Card N3000

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ID 683040
Date 6/14/2021
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. System Requirements 3. Hardware Installation 4. Installing the OPAE Software 5. OPAE Tools 6. Sample Test: Native Loopback 7. Installing the Intel XL710 Driver 8. Configuring Ethernet Interfaces 9. Testing Network Loopback Using Data Plane Development Kit (DPDK) 10. Graceful Shutdown 11. Single Event Upset (SEU) 12. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000 A. Troubleshooting B. Upgrade your Intel® FPGA PAC N3000 with Production Version of BMC and Intel® Arria® 10 Image C. Configure the 4.19 Kernel D. fpgabist Sample Output
1. About this Document x
1.1. Acronym List
2. System Requirements x
2.1. Cooling Requirements
3. Hardware Installation x
3.1. Installing the Intel® FPGA PAC N3000
4. Installing the OPAE Software x
4.1. Install Additional Packages 4.2. Install the Release Package 4.3. Identify the Intel® MAX® 10 Version on your Intel® FPGA PAC N3000
4.2. Install the Release Package x
4.2.1. Remove Previous OPAE Packages 4.2.2. Install the Acceleration Stack for Runtime 4.2.3. Install the Acceleration Stack for Development 4.2.4. Verify the OPAE Installation 4.2.5. Install the Configuration Files
4.3. Identify the Intel® MAX® 10 Version on your Intel® FPGA PAC N3000 x
4.3.1. FPGA Factory Image Overview
5. OPAE Tools x
5.1. Using fpgasupdate 5.2. Using fpgainfo 5.3. Test PCIe and External Memories with fpgabist 5.4. Test Network Loopback using fpgadiag
7. Installing the Intel XL710 Driver x
7.1. Updating the Intel XL710 Firmware
8. Configuring Ethernet Interfaces x
8.1. Modifying the Interface Maximum Transmission Unit (MTU) Size 8.2. Setting Forward Error Correction (FEC) Mode 8.3. Ethernet Pause Flow Control 8.4. Get Link Status and Statistics
9. Testing Network Loopback Using Data Plane Development Kit (DPDK) x
9.1. Test Using an External Traffic Generator 9.2. Test Using a Packet Generator 9.3. Troubleshooting in DPDK 9.4. Revert Back from DPDK to OPAE
10. Graceful Shutdown x
10.1. Background 10.2. Using OPAE 10.3. Using DPDK
11. Single Event Upset (SEU) x
11.1. OPAE Handling of SEU 11.2. DPDK Handling of SEU
A. Troubleshooting x
A.1. If OPAE installation verification fails, how to install OPAE manually?
B. Upgrade your Intel® FPGA PAC N3000 with Production Version of BMC and Intel® Arria® 10 Image x
B.1. Upgrading from 1.1 Beta to Production Version B.2. Upgrading from 1.1 Alpha-2 or Older to Production Version
B.1. Upgrading from 1.1 Beta to Production Version x
B.1.1. Root Entry Hash Programmed B.1.2. Root Entry Hash Not Programmed
D. fpgabist Sample Output x
D.1. For 2x2x25G Configuration D.2. For 8x10G Configuration
1. About this Document
2. System Requirements
3. Hardware Installation
4. Installing the OPAE Software
5. OPAE Tools
6. Sample Test: Native Loopback
7. Installing the Intel XL710 Driver
8. Configuring Ethernet Interfaces
9. Testing Network Loopback Using Data Plane Development Kit (DPDK)
10. Graceful Shutdown
11. Single Event Upset (SEU)
12. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000
A. Troubleshooting
B. Upgrade your Intel® FPGA PAC N3000 with Production Version of BMC and Intel® Arria® 10 Image
C. Configure the 4.19 Kernel
D. fpgabist Sample Output

B.1.1. Root Entry Hash Programmed

  1. Sign the provided Intel® Arria® 10 image located at /usr/share/opae/n3000/one-time-update/<25G or 10G>/chip_rsu-*-user-rollback-unsigned.bin with valid code signing key and SR root key using the PACSign and name the output file as chip_rsu-*-user-rollback-signed.bin.
  2. Copy the signed Intel® Arria® 10 image to location: /usr/share/opae/n3000/one-time-update/*/ 
    $ cp chip_rsu-*-user-rollback-signed.bin /usr/share/opae/n3000/\
one-time-update/<25G or 10G>/
  3. Reflect the signed Intel® Arria® 10 image name in the rollback manifest file:
    $ vim /usr/share/opae/n3000/one-time-update/<25G or 10G>/rollback-*.json
    Change the filename field under flash to reflect the signed bitstream name, for example: 
    "flash": [
        {
            "enabled": true,
            "filename": "chip_rsu-8x10G-user-rollback-signed.bin",
            "force": false,
            "secure": true,
            "timeout": "45m",
            "type": "user",
            "version": "0x0021064001020134"
        },
  4. Rollback the Intel® MAX® 10 and Intel® Arria® 10 image to allow upgrade:
    $ sudo super-rsu /usr/share/opae/n3000/one-time-update/<25G or 10G>/\
rollback-*.json --with-rsu

    $ sudo fpgainfo fme
    Note: The Intel® MAX® 10 build version will be 111.2.13 after performing rollback. 
    $ ls -l /sys/class/fpga/intel-fpga-dev.*/intel-fpga-fme.*/\
spi-altera.*.auto/spi_master/spi*/spi*/intel-generic-qspi.*.auto/
    This sysfs entry must exist.
  5. Run the One-Time Secure Update (OTSU):
    $ sudo fpgaotsu /usr/share/opae/n3000/one-time-update/<25G or 10G>/\
otsu-*.json --rsu
    If OTSU fails, run the fpgainfo fme to find out the Intel® MAX® 10 build version and take appropriate action as stated:
    Intel® MAX® 10 Build Version Action
    D.111.2.13 Repeat OTSU
    D.2.0.6 Run command:
    sudo super-rsu /usr/share/opae/n3000/super-rsu/<2x2x25G or 8x10G or 4x25G>/super-rsu-*.json --with-rsu
  6. To verify successful OTSU:
    sudo fpgaotsu /usr/share/opae/n3000/one-time-update/<25G or 10G>/\
otsu-*.json --verify
    At this point, the Intel® FPGA PAC N3000 will have the following Intel® Arria® 10 image, Intel® MAX® 10 NIOS FW and Intel® MAX® 10 Build versions.
    Configuration User Partition Image Bitstream ID PR interface ID Intel® MAX® 10 NIOS FW Intel® MAX® 10 BUILD
    2x2x25G 4x25G 0x2300110010309 f3c99413-5081-4aad-bced-07eb84a6d0bb D.2.0.19 D.2.0.6
    4x25G
    8x10G 8x10G 0x2300010010309 901dd697-ca79-4b05-b843-8138cefa2846 D.2.0.19 D.2.0.6
    Important: The 2x2x25G or 4x25G Configuration Installer loads the FPGA flash user partition with 4x25G Intel provided factory test image and loads factory partition with 2x2x25G Intel provided factory test image. The 8x10 Configuration Installer loads both the user and factory FPGA flash partitions with 8x10G Intel provided factory test image.
  7. Install the PV 1.1 Patch.
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