F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 6/26/2023
Public

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Document Table of Contents

4.4.9. UI Value and PMA Delay

Table 23.  UI Value and PMA Delay of Ethernet Modes
FEC type:
  • No FEC: No FEC
  • CL74: IEEE 802.3 BASE-R Firecode (CL74)
  • CL91: IEEE 802.3 RS(528,514) (CL91)
  • CL134: IEEE 802.3 RS(544,514) (CL134)
  • ETC: Ethernet Technology Consortium ETC RS(272, 258)
PMA Rate (Gbps) Ethernet Mode FEC Type UI Value Simulation PMA Delay (UI) Hardware PMA Delay 16 (UI)
ps {4-bit ns, 28-bit fractional ns} FGT FHT FGT FHT
TX RX TX RX TX RX TX RX
10.3125 10GE-1 No FEC 96.9697 32’h018D3019 80 88 276 295 79 88 320 282
25.78125 25GE-1

No FEC

CL74

CL91

38.7878 32'h009EE00A
25.78125

50GE-2

100GE-4

No FEC

CL91

26.5625

50GE-2

100GE-4

200GE-8

CL134

37.6471 32'h009A33CD
53.125

50GE-1

100GE-2

200GE-4

400GE-8

CL134

ETC

18.8235 32'h004D19EC 158 176 552 589 158 175 640 584
106.25

100GE-1

200GE-2

400GE-4

CL134

9.4118 32'h00268CF3 N/A N/A 1,094 1,037 N/A N/A 1,186 1,124
Table 24.  Number of Virtual Lanes per Ethernet Speed
Ethernet Speed Number of Virtual Lanes (VL)
10GE 1
25GE 1
50GE 4
100GE 20
200GE 8
400GE 16
16 The hardware PMA delay values are preliminary and subject to change.