F-Tile Ethernet Intel® FPGA Hard IP User Guide

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ID 683023
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History for F-Tile Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Round-trip Latency 1.2.5. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion 4.2.1.7. TX Packing Logic
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode 4.4.11. Routing Delay Adjustment for Basic Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. Deterministic Latency Interface 7.13. 32-bit Soft CWBIN Counters 7.14. Reconfiguration Interfaces 7.15. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.12. Deterministic Latency Interface x
7.12.1. Deterministic Latency Measurement
7.14. Reconfiguration Interfaces x
7.14.1. Ethernet Reconfiguration Interfaces 7.14.2. Transceiver Reconfiguration Interfaces
7.15. Precision Time Protocol Interface x
7.15.1. Time-of-Day Interface 7.15.2. TX 2-Step Timestamp Interface 7.15.3. TX 1-Step Timestamp Interface 7.15.4. RX Timestamp Interface 7.15.5. PTP Status Interface 7.15.6. PTP Tile Interface
7.15.3. TX 1-Step Timestamp Interface x
7.15.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History for F-Tile Ethernet Intel® FPGA Hard IP User Guide

4.4.3.1. PTP TX Client Flow

In this section, the acronyms PL and VL stand for Physical Lane and Virtual Lane respectively.

The following flows depict pseudo-code meant for the conceptual, illustrative purposes. For definitive software routines, refer to the design example.

Important: If IP undergoes TX reset at any point in this flow, you must restart the entire PTP TX client flow.
  1. After power up or a TX reset, wait until TX raw offset data are ready.
    You can monitor the status via one of the following:
    • Output port:
      o_tx_ptp_offset_data_valid = 1'b1
    • Polling via Avalon® memory-mapped interface register until it is asserted:
      csr_read(ptp_status.tx_ptp_offset_data_valid) = 1’b1
  2. Read TX raw offset data from IP:
    tx_const_delay      = csr_read(ptp_tx_lane_calc_data_constdelay[30:0])
tx_const_delay_sign = csr_read(ptp_tx_lane_calc_constdelay[31])

for (pl = 0; pl < PL; pl++) {
 tx_apulse_offset[pl] = csr_read(ptp_tx_lane<pl>_calc_data_offset[30:0])
 tx_apulse_offset_sign[pl] = csr_read(ptp_tx_lane<pl>_calc_data_offset[31])
 tx_apulse_wdelay[pl] = csr_read(ptp_tx_lane<pl>_calc_data_wiredelay[19:0])
 tx_apulse_time[pl]   = csr_read(ptp_tx_lane<pl>_calc_data_time[27:0])
}
  3. Determine TX reference lane:

    The following sub-steps apply for designs with multiple lanes since any lane can be used as reference lane. You can skip the sub-steps for designs with one single PMA lane by setting the tx_ref_pl = 0.

    1. Detect rollover of asynchronous pulse time:

      The tx_apulse_time[pl] signal represents an asynchronous time of each physical lane in a 28-bit format, where bit [27:16] represent asynchronous pulse time in nanoseconds (ns) and bit [15:0] represent asynchronous pulse time in fractional nanoseconds (fns).

      Two types of rollover are possible:
      1. Natural rollover from bit 27 to bit 28 when the value reaches 28'hFFF_FFFF. Before rollover, bit [27:24] is 4'hF.
      2. Billion rollover when the TOD reaches one billion ns or 48'h3B9A_CA00_0000 in hex value. Before rollover, bit [27:24] is 4'h9.
      Given tx_apulse_time_max is largest tx_apulse_time from all physical lanes,
for (pl = 0; pl < PL; pl++){
  if (tx_apulse_time_max - tx_apulse_time[pl] > 29'h01F4_0000){
    tx_apulse_time[pl] = tx_apulse_time[pl] + 29'h1000_0000
  } else {
    tx_apulse_time[pl] = tx_apulse_time[pl] + 29'h0A00_0000
  }
}
    2. Calculate the actual time of TX Alignment Marker at TX PMA parallel data interface. 
      for (pl = 0; pl < PL; pl++) {
 tx_am_actual_time[pl] = 
   (tx_apulse_time[pl]) 
 + (tx_apulse_offset_sign[pl] ? –tx_apulse_offset[pl] 
                               : tx_apulse_offset[pl])
 – (tx_apulse_wdelay[pl])
}
    3. Determine TX reference lane:
      tx_ref_pl = pl
      The TX reference lane is the TX physical lane containing the largest tx_am_actual_time when comparing among all physical lanes.
  4. Calculate TX offsets:
    Attention: Step 4c is not applicable for 10G and 25G Ethernet data rates. You must skip step 4c for these rates.
    1. Calculate TX TAM adjust:
      tx_tam_adjust_sim = 
  (tx_const_delay_sign ? –tx_const_delay : tx_const_delay)
+ (tx_apulse_offset_sign[tx_ref_pl] ? 
      –tx_apulse_offset[tx_ref_pl] : tx_apulse_offset[tx_ref_pl])
– (tx_apulse_wdelay[tx_ref_pl])
      For hardware run with PTP Timestamp accuracy mode set to Advanced: 
      tx_tam_adjust = (tx_tam_adjust_sim) 
+ (tx_routing_adj_sign[tx_ref_pl] ? – tx_routing_adj[tx_ref_pl] 
                                    : tx_routing_adj[tx_ref_pl])
      For routing delay adjustment information, refer to the Routing Delay Adjustment for Advanced Timestamp Accuracy Mode section.
      For all other cases: 
      tx_tam_adjust = tx_tam_adjust_sim

      Convert TAM adjust to a 32-bit 2's complement number:

      tx_tam_adjust_2c = tx_tam_adjust
where tx_tam_adjust is a 32-bit 2's complement number
    2. Calculate TX extra latency:
      Convert unit of TX PMA delay from UI to nanoseconds. For UI value, refer to tables specified in UI Value and PMA Delay. 
      tx_pma_delay_ns = tx_pma_delay_ui * UI13
      TX extra latency is a positive adjustment. To indicate the positive adjustment, set the most-significant register bit to 0. Total up all extra latency together: 
      tx_extra_latency[31] = 0
tx_extra_latency[30:0] = tx_pma_delay_ns + tx_external_phy_delay
    3. Calculate TX virtual lane offsets:

      Use VL0 as the reference virtual lane. Assign TX virtual lane offset values according to virtual lane order.

      • For KP-FEC or LL-FEC variants:
        Note: % is the modulo operator.

for (vl = 0; vl < VL; vl++) {
   tx_vl_offset[vl] = [vl - (vl % PL)] / PL * 68 * UI13
}
      • For KR-FEC variants:
        for (vl = 0; vl < VL; vl++) {
   tx_vl_offset[vl] = [vl - (vl % PL)] / PL * 66 * UI13
}
      • For no FEC variants:
        for (vl = 0; vl < VL; vl++) {
   tx_vl_offset[vl] = [vl - (vl % PL)] / PL * 1 * UI13
}
  5. Write the determined TX reference lane into IP:
    csr_write (ptp_ref_lane.tx_ref_lane, tx_ref_pl)
  6. Write the calculated TX offsets to IP:
    Attention: Step 6a is not applicable for 10G and 25G Ethernet data rates. You must skip step 6a for these rates.
    1. Write TX virtual lane offsets:
      for (vl = 0; vl < VL; vl++) {
   csr_write(tx_ptp_vl_offset_<vl>, tx_vl_offset[vl])
}
    2. Write TX extra latency:
      csr_write(tx_ptp_extra_latency, tx_extra_latency)
    3. Write TX TAM adjust:
      csr_write(ptp_tx_tam_adjust, tx_tam_adjust_2c)
  7. Notify soft PTP that uses flow configuration is completed. 
    csr_write(ptp_tx_user_cfg_status.tx_user_cfg_done, 1'b1)
  8. UI value measurement. Follow the steps mentioned in the TX UI Adjustment section..

    For simulation or hardware run with 0 ppm setup, you can skip the measurement and program 0 ppm UI value defined in UI Adjustment.

  9. Wait until TX PTP is ready.
    You can monitor the status via one of the following:
    • Output port:
      o_tx_ptp_ready = 1'b1
    • Polling via CSR:
      csr_read(ptp_status.tx_ptp_ready) = 1’b1
  10. TX PTP is up and running.
    1. Adjust TX UI value.

      Perform the TX UI adjustment occasionally to prevent time counter drift from golden time-of-day in the system. Follow the steps described in TX UI Adjustment .

      Note: UI measurement is a long process in simulation. Therefore, for simulation, Intel recommends skipping this step and program a 0 ppm value.
Related Information
13 The UI format differs from the format of other variables. UI uses the {4-bit ns, 28-bit fractional ns} format. Other variables defined in this flow use the {N-bit ns, 16-bit fractional ns} format, where N is the largest number to store the calculation's max value. If you use UI format in your calculation, you must convert your result to a 16-bit fractional ns format.
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