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Ixiasoft
Visible to Intel only — GUID: kgn1614087408057
Ixiasoft
4.4.3.1. PTP TX Client Flow
In this section, the acronyms PL and VL stand for Physical Lane and Virtual Lane respectively.
The following flows depict pseudo-code meant for the conceptual, illustrative purposes. For definitive software routines, refer to the design example.
- After power up or a TX reset, wait until TX raw offset data are ready.
You can monitor the status via one of the following:
- Output port:
o_tx_ptp_offset_data_valid = 1'b1
- Polling via Avalon® memory-mapped interface register until it is asserted:
csr_read(ptp_status.tx_ptp_offset_data_valid) = 1’b1
- Output port:
- Read TX raw offset data from IP:
tx_const_delay = csr_read(ptp_tx_lane_calc_data_constdelay[30:0]) tx_const_delay_sign = csr_read(ptp_tx_lane_calc_constdelay[31]) for (pl = 0; pl < PL; pl++) { tx_apulse_offset[pl] = csr_read(ptp_tx_lane<pl>_calc_data_offset[30:0]) tx_apulse_offset_sign[pl] = csr_read(ptp_tx_lane<pl>_calc_data_offset[31]) tx_apulse_wdelay[pl] = csr_read(ptp_tx_lane<pl>_calc_data_wiredelay[19:0]) tx_apulse_time[pl] = csr_read(ptp_tx_lane<pl>_calc_data_time[27:0]) }
- Determine TX reference lane:
The following sub-steps apply for designs with multiple lanes since any lane can be used as reference lane. You can skip the sub-steps for designs with one single PMA lane by setting the tx_ref_pl = 0.
- Detect rollover of asynchronous pulse time:
The tx_apulse_time[pl] signal represents an asynchronous time of each physical lane in a 28-bit format, where bit [27:16] represent asynchronous pulse time in nanoseconds (ns) and bit [15:0] represent asynchronous pulse time in fractional nanoseconds (fns).
Two types of rollover are possible:- Natural rollover from bit 27 to bit 28 when the value reaches 28'hFFF_FFFF. Before rollover, bit [27:24] is 4'hF.
- Billion rollover when the TOD reaches one billion ns or 48'h3B9A_CA00_0000 in hex value. Before rollover, bit [27:24] is 4'h9.
Given tx_apulse_time_max is largest tx_apulse_time from all physical lanes, for (pl = 0; pl < PL; pl++){ if (tx_apulse_time_max - tx_apulse_time[pl] > 29'h01F4_0000){ tx_apulse_time[pl] = tx_apulse_time[pl] + 29'h1000_0000 } else { tx_apulse_time[pl] = tx_apulse_time[pl] + 29'h0A00_0000 } }
- Calculate the actual time of TX Alignment Marker at TX PMA parallel data interface.
for (pl = 0; pl < PL; pl++) { tx_am_actual_time[pl] = (tx_apulse_time[pl]) + (tx_apulse_offset_sign[pl] ? –tx_apulse_offset[pl] : tx_apulse_offset[pl]) – (tx_apulse_wdelay[pl]) }
- Determine TX reference lane:
tx_ref_pl = pl
The TX reference lane is the TX physical lane containing the largest tx_am_actual_time when comparing among all physical lanes.
- Detect rollover of asynchronous pulse time:
- Calculate TX offsets:
Attention: Step 4c is not applicable for 10G and 25G Ethernet data rates. You must skip step 4c for these rates.
- Calculate TX TAM adjust:
tx_tam_adjust_sim = (tx_const_delay_sign ? –tx_const_delay : tx_const_delay) + (tx_apulse_offset_sign[tx_ref_pl] ? –tx_apulse_offset[tx_ref_pl] : tx_apulse_offset[tx_ref_pl]) – (tx_apulse_wdelay[tx_ref_pl])
For hardware run with PTP Timestamp accuracy mode set to Advanced:tx_tam_adjust = (tx_tam_adjust_sim) + (tx_routing_adj_sign[tx_ref_pl] ? – tx_routing_adj[tx_ref_pl] : tx_routing_adj[tx_ref_pl])
For routing delay adjustment information, refer to the Routing Delay Adjustment for Advanced Timestamp Accuracy Mode section.For all other cases:tx_tam_adjust = tx_tam_adjust_sim
Convert TAM adjust to a 32-bit 2's complement number:
tx_tam_adjust_2c = tx_tam_adjust where tx_tam_adjust is a 32-bit 2's complement number
- Calculate TX extra latency:
Convert unit of TX PMA delay from UI to nanoseconds. For UI value, refer to tables specified in UI Value and PMA Delay.
tx_pma_delay_ns = tx_pma_delay_ui * UI13
TX extra latency is a positive adjustment. To indicate the positive adjustment, set the most-significant register bit to 0. Total up all extra latency together:tx_extra_latency[31] = 0 tx_extra_latency[30:0] = tx_pma_delay_ns + tx_external_phy_delay
- Calculate TX virtual lane offsets:
Use VL0 as the reference virtual lane. Assign TX virtual lane offset values according to virtual lane order.
- For KP-FEC or LL-FEC variants:
Note: % is the modulo operator. for (vl = 0; vl < VL; vl++) { tx_vl_offset[vl] = [vl - (vl % PL)] / PL * 68 * UI13 }
- For KR-FEC variants:
for (vl = 0; vl < VL; vl++) { tx_vl_offset[vl] = [vl - (vl % PL)] / PL * 66 * UI13 }
- For no FEC variants:
for (vl = 0; vl < VL; vl++) { tx_vl_offset[vl] = [vl - (vl % PL)] / PL * 1 * UI13 }
- For KP-FEC or LL-FEC variants:
- Calculate TX TAM adjust:
- Write the determined TX reference lane into IP:
csr_write (ptp_ref_lane.tx_ref_lane, tx_ref_pl)
- Write the calculated TX offsets to IP:
Attention: Step 6a is not applicable for 10G and 25G Ethernet data rates. You must skip step 6a for these rates.
- Write TX virtual lane offsets:
for (vl = 0; vl < VL; vl++) { csr_write(tx_ptp_vl_offset_<vl>, tx_vl_offset[vl]) }
- Write TX extra latency:
csr_write(tx_ptp_extra_latency, tx_extra_latency)
- Write TX TAM adjust:
csr_write(ptp_tx_tam_adjust, tx_tam_adjust_2c)
- Write TX virtual lane offsets:
- Notify soft PTP that uses flow configuration is completed.
csr_write(ptp_tx_user_cfg_status.tx_user_cfg_done, 1'b1)
- UI value measurement. Follow the steps mentioned in the TX UI Adjustment section..
For simulation or hardware run with 0 ppm setup, you can skip the measurement and program 0 ppm UI value defined in UI Adjustment.
- Wait until TX PTP is ready.
You can monitor the status via one of the following:
- Output port:
o_tx_ptp_ready = 1'b1
- Polling via CSR:
csr_read(ptp_status.tx_ptp_ready) = 1’b1
- Output port:
- TX PTP is up and running.
- Adjust TX UI value.
Perform the TX UI adjustment occasionally to prevent time counter drift from golden time-of-day in the system. Follow the steps described in TX UI Adjustment .
Note: UI measurement is a long process in simulation. Therefore, for simulation, Intel recommends skipping this step and program a 0 ppm value.
- Adjust TX UI value.