Visible to Intel only — GUID: GUID-4096E831-F7A4-4B3A-A74E-D104CC647C61
Visible to Intel only — GUID: GUID-4096E831-F7A4-4B3A-A74E-D104CC647C61
arch
Tells the compiler which features it may target, including which instruction sets it may generate.
Syntax
Linux: |
-arch code |
macOS: |
-arch code |
Windows: |
/arch:code |
Arguments
code |
Indicates to the compiler a feature set that it may target, including which instruction sets it may generate. Many of the following descriptions refer to Intel® Streaming SIMD Extensions (Intel® SSE) and Supplemental Streaming SIMD Extensions (SSSE). Possible values are:
|
Default
varies |
If option arch is not specified, the default target architecture supports Intel® SSE2 instructions. |
Description
This option tells the compiler which features it may target, including which instruction sets it may generate.
Code generated with these options should execute on any compatible, non-Intel processor with support for the corresponding instruction set.
Options /arch and /Qx are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning.
If you specify both the /Qax and /arch options, the compiler will not generate Intel-specific instructions.
This option only applies to host compilation. When offloading is enabled, it does not impact device-specific compilation. Offloading can only be enabled when using ifx.
For compatibility with Compaq* Visual Fortran, the ifort compiler allows the following keyword values. However, you should use the suggested replacements.
Compatibility Value |
Suggested Replacement on Linux* and Windows* (ifort only) |
pn1 |
-mia32 or /arch:IA32 |
pn2 |
-mia32 or /arch:IA32 |
pn3 |
-mia32 or /arch:IA32 |
pn4 |
-msse2 or /arch:SSE2 |
IDE Equivalent
Visual Studio: Code Generation > Enable Enhanced Instruction Set
Alternate Options
None