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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. PCS Direct Signals: IEEE
3.4.6. PCS Direct Signals: IEEE_FLEXE_66/PCS66
3.4.7. Custom Cadence Control and Status Signals
3.4.8. RX PMA Status Signals
3.4.9. TX and RX PMA and Core Interface FIFO Signals
3.4.10. Avalon Memory-Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. Run-time Reset Sequence—TX with FEC
3.8.8. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.9. TX PLL Lock Loss
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
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1. GTS Transceiver Overview
Updated for: |
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Intel® Quartus® Prime Design Suite 24.2 |
This user guide describes the architecture and implementation details about the GTS transceivers in Agilex™ 5 FPGAs.
- Architecture details of the GTS transceiver in chapter 2
- Implementation details of the GTS IPs in chapter 3 to 6.
The GTS transceivers have a non-return-to-zero (NRZ) serial interface with an advanced physical medium attachment (PMA) and multiple hard IPs to allow efficient implementation of popular and emerging serial protocols. The GTS transceiver banks are monolithically integrated to the FPGA core for greater efficiency in lower power consumption and smaller form factor.
Note: Device support for Agilex™ 5 D-Series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 24.2 is restricted. To enable D-Series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Altera sales representative.
Feature | E-Series (Device Group B) | E-Series (Device Group A) | D-Series |
---|---|---|---|
Number of available PMAs | 4-24 PMAs | 8-32 PMAs | |
Data rate range | 1-17.16 Gbps NRZ | 1-28.1 Gbps NRZ | |
PCIe* hard IP | Up to six PCIe* 3.0 x4 or PCIe* 4.0 x4 1 | Up to six PCIe* 4.0 x4 | Up to four PCIe* 4.0 x8 |
Ethernet hard IP | IEEE 802.3-compliant Clause 49 physical coding sublayer (PCS) | IEEE 802.3-compliant Clause 49 or Clause 107 PCS | |
Up to six 10 Gigabit Ethernet (GbE) media access control (MAC) | Up to six 10 or 25 GbE MAC | Up to sixteen 10 or 25 GbE MAC | |
Supports IEEE 1588 Precision Time Protocol (PTP), Auto Negotiation and Link Training (AN/LT) | |||
Forward Error Correction (FEC) |
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USB 3.1 hard IP 2 | One channel with USB 3.1 controller in HPS block |
1 Supported for -4S speed grade (VCC=0.8V) devices only.
2 Devices with GTS transceiver and HPS only.