AN 791: Migrating the Avalon® Streaming Interface for PCI Express* to Intel® Stratix® 10 Devices

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ID 683036
Date 9/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences 4. Document Revision History for AN-791
3. Interface and Signal Differences x
3.1. Clock Interface 3.2. Avalon-ST TX Interface 3.3. Avalon-ST TX Credit Interface 3.4. Avalon-ST RX Interface 3.5. Status and Link Training Interface 3.6. Configuration Status Interface 3.7. Interrupt Interface 3.8. Error Interface 3.9. Reset 3.10. PHY Interface for PCI Express (PIPE) Interface 3.11. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
4. Document Revision History for AN-791

1. Introduction

Updated for:
Intel® Quartus® Prime Design Suite Quartus Prime Pro v17.1 Stratix 10 Editions
This design migration reference guide describes differences in PCI Express* implementations between the Intel® Arria® 10 (or Stratix® V) and Intel® Stratix® 10 device families. It should ease migration from those earlier device families to Intel® Stratix® 10 devices.

The Intel® Stratix® 10 implementation provides many new features. In addition, the interfaces and functions are different than the Intel® Arria® 10 and Stratix® V IP cores.

This design migration reference guide covers migration for the Avalon® Streaming (Avalon-ST) interface. A separate design migration reference guide covers the Avalon® Memory-Mapped (Avalon-MM) and Avalon-MM with DMA interfaces.

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