PeriphPll_grp Address Map

Contains registers with settings for the Peripheral PLL.
Module Instance Base Address End Address
i_clk_mgr_perpllgrp 0xFFD100A4 0xFFD10123
Register Offset Width Access Reset Value Description
en 0x0 32 RW 0x00000FFF 
Enable Register
ens 0x4 32 RW 0x00000FFF 
Enable Set Register
enr 0x8 32 RW 0x00000FFF 
Enable Reset Register
bypass 0xC 32 RW 0x000000FF 
Bypass Register
bypasss 0x10 32 RW 0x000000FF 
Bypass Set Register
bypassr 0x14 32 RW 0x000000FF 
Bypass Reset Register
cntr2clk 0x18 32 RW 0x00010001 
Peripheral PLL Control Register for Counter 2 Clock
cntr3clk 0x1C 32 RW 0x00010001 
Peripheral PLL Control Register for Counter 3 Clock
cntr4clk 0x20 32 RW 0x00010004 
Peripheral PLL Control Register for Counter 4 Clock
cntr5clk 0x24 32 RW 0x00000001 
Peripheral PLL Control Register for Counter 5 Clock
cntr6clk 0x28 32 RW 0x00000001 
Peripheral PLL Control Register for Counter 6 Clock
cntr7clk 0x2C 32 RW 0x00000000 
Peripheral PLL Control Register for Counter 7 Clock
cntr8clk 0x30 32 RW 0x00010000 
Peripheral PLL Control Register for Counter 8 Clock
cntr9clk 0x34 32 RW 0x00010000 
periph PLL Control Register for Counter 10 Clock
emacctl 0x38 32 RW 0x00000000 
Main Divide Register
gpiodiv 0x3C 32 RW 0x00000001 
GPIO Divide Register
pllglob 0x40 32 RW 0x00000100 
This refects register settings for both the channels of the periph PLL
fdbck 0x44 32 RW 0x22000000 
VCO freq register counters
mem 0x48 32 RW 0x00000000 
Registers dealing with PLL internal memory access.
memstat 0x4C 32 RW 0x00000000 
Periph PLL memstatus register. contains ack and memory read data
pllc0 0x50 32 RW 0x08000002 
Channel C0 frequency settings for the periph PLL
pllc1 0x54 32 RW 0x01000004 
Channel C1 settings for the periph PLL
vcocalib 0x58 32 RW 0x00000ABF 
VCO calibration control registers.