fdbck

         VCO freq register counters

Module Instance	Base Address	Register Address
`i_clk_mgr_perpllgrp`	`0xFFD100A4`	`0xFFD100E8`

Size: 32

Offset: 0x44

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`mdiv` `RW 0x22`								`fdiv` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`fdiv` `RW 0x0`

fdbck Fields

Bit	Name	Description	Access	Reset
31:24	`mdiv`	Feedback Clock Divider. The Pll Initially Operates At The Frequency Based On The Mdiv And Fdiv Values Set At Reset. After Pll Exits Reset, Any Change In Mdiv Or Fdiv Values At The Interface Are Stored Internally. ictl_vpll_mdiv_a_[7:0] = (Fvco /( Fref / ictl_vpll_refdiv_nt_[5:0])) – 6. Fref_eff = (Fref)/(refdiv[5:0]) Frq_mul = {(6+ mdiv[7:0]* (fdiv[23:0]/ (2^24)))} Fsyn = Frq_mul * Fref_eff (Fsyn /6) >= 3* Fref_eff Fock_vpll_pr1 = Fsyn /(pr1[7:0])	`RW`	`0x22`
23:0	`fdiv`	Fractional Synthesizer Center Frequency Control Word. The PLL Initially Operates At The Frequency Based On The Mdiv Value Set At Reset. After Pll Exits Reset, Any Change In Mdiv Value At The Interface Is Stored Internally. Fref_eff = (Fref)/(refdiv[5:0]) Frq_mul = {(6+ mdiv[7:0]* (fdiv[23:0]/ (2^24)))} Fsyn = Frq_mul * Fref_eff (Fsyn /6) >= 3* Fref_eff Fock_vpll_pr1 = Fsyn /(pr1[7:0])	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:24

mdiv

Feedback Clock Divider. The Pll Initially Operates At The Frequency Based On The Mdiv And Fdiv Values Set At Reset. After Pll Exits Reset, Any Change In Mdiv Or Fdiv Values At The Interface Are Stored Internally. ictl_vpll_mdiv_a_[7:0] = (Fvco /( Fref / ictl_vpll_refdiv_nt_[5:0])) – 6. 
Fref_eff    = (Fref)/(refdiv[5:0])
Frq_mul = {(6+ mdiv[7:0]* (fdiv[23:0]/ (2^24)))}
Fsyn = Frq_mul * Fref_eff    
(Fsyn /6) >= 3* Fref_eff    

Fock_vpll_pr1   =    Fsyn /(pr1[7:0])

RW

0x22

23:0

fdiv

Fractional Synthesizer Center Frequency Control Word. The PLL Initially Operates At The Frequency Based On The Mdiv Value Set At Reset. After Pll Exits Reset, Any Change In Mdiv Value At The Interface Is Stored Internally. 
Fref_eff    = (Fref)/(refdiv[5:0])
Frq_mul = {(6+ mdiv[7:0]* (fdiv[23:0]/ (2^24)))}
Fsyn = Frq_mul * Fref_eff    
(Fsyn /6) >= 3* Fref_eff    

Fock_vpll_pr1   =    Fsyn /(pr1[7:0])

RW

0x0