enr 

         Write One to Clear corresponding fields in Enable Register.
Module Instance Base Address Register Address
i_clk_mgr_perpllgrp 0xFFD100A4 0xFFD100AC

Size: 32

Offset: 0x8

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

nandclken

RW 0x1

spimclken

RW 0x1

usbclken

RW 0x1

psiclken

RW 0x1

s2fuser1clken

RW 0x1

sdmmcclken

RW 0x1

gpiodben

RW 0x1

emacptpen

RW 0x1

emac2en

RW 0x1

emac1en

RW 0x1

emac0en

RW 0x1

enr Fields

Bit Name Description Access Reset
10 nandclken 
Enables NAND peripheral clock.   This enable goes outside of the Clock Manger to the NAND directly.
 RW 0x1
9 spimclken 
Enables SPI Master peripheral clock.   This enable goes outside of the Clock Manger to the SPIM directly.
 RW 0x1
8 usbclken 
Enables USB peripheral clock.   This enable goes outside of the Clock Manger to the USB directly.
 RW 0x1
7 psiclken 
Enables psi_ref clock.
RW 0x1
6 s2fuser1clken 
Enables clock s2f_user1_clk output
 RW 0x1
5 sdmmcclken 
Enables SDMMC peripheral clock.   This enable goes outside of the Clock Manger to the SDMMC directly.
 RW 0x1
4 gpiodben 
Enables clock gpio_db_clk output
 RW 0x1
3 emacptpen 
Enables clock emac_ptp_clk output
 RW 0x1
2 emac2en 
Enables clock emac2_clk output
 RW 0x1
1 emac1en 
Enables clock emac1_clk output
 RW 0x1
0 emac0en 
Enables clock emac0_clk output
 RW 0x1