cntr3clk 

         Contains settings that control Counter 3 clock generated from the Peripheral PLL VCO clock.
Module Instance Base Address Register Address
i_clk_mgr_perpllgrp 0xFFD100A4 0xFFD100C0

Size: 32

Offset: 0x1C

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

src

RW 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cnt

RW 0x1

cntr3clk Fields

Bit Name Description Access Reset
18:16 src 
Selects the source for the active 5:1 clock selection when the PLL is not bypassed.
Value Description
0 MAIN
1 PERI
2 OSC1
3 INTOSC
4 FPGA
RW 0x1
10:0 cnt 
Divides the VCO frequency by the value+1 in this field.
 RW 0x1