gpiodiv

         Contains a field that controls the clock divider for the GPIO De-bounce clock.

Module Instance	Base Address	Register Address
`i_clk_mgr_perpllgrp`	`0xFFD100A4`	`0xFFD100E0`

Size: 32

Offset: 0x3C

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`gpiodbclk` `RW 0x1`

gpiodiv Fields

Bit	Name	Description	Access	Reset
15:0	`gpiodbclk`	The gpio_db_clk is divided down from the periph_base_clk by the value plus one specified in this field. The value 0 (divide by 1) is illegal. A value of 1 indicates divide by 2, 2 divide by 3, etc.	`RW`	`0x1`