Dedicated_PinMux Summary

HPS Pinmux CSR.

Base Address: 0xFFD13000

Register Address Offset	Bit Fields
`i_dedio_pinmux_csr`
`pin0sel` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin1sel` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin2sel` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin3sel` `0xC` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin4sel` `0x10` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin5sel` `0x14` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin6sel` `0x18` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin7sel` `0x1C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin8sel` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin9sel` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin10sel` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin11sel` `0x2C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin12sel` `0x30` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin13sel` `0x34` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin14sel` `0x38` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin15sel` `0x3C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin16sel` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin17sel` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin18sel` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin19sel` `0x4C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin20sel` `0x50` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin21sel` `0x54` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin22sel` `0x58` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin23sel` `0x5C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin24sel` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin25sel` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin26sel` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin27sel` `0x6C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin28sel` `0x70` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin29sel` `0x74` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin30sel` `0x78` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin31sel` `0x7C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin32sel` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin33sel` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin34sel` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin35sel` `0x8C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin36sel` `0x90` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin37sel` `0x94` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin38sel` `0x98` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin39sel` `0x9C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin40sel` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin41sel` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin42sel` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin43sel` `0x10C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin44sel` `0x110` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin45sel` `0x114` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin46sel` `0x118` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`pin47sel` `0x11C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`val` `RW 0x9`
`io0ctrl` `0x130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io1ctrl` `0x134` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io2ctrl` `0x138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io3ctrl` `0x13C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io4ctrl` `0x140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io5ctrl` `0x144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io6ctrl` `0x148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io7ctrl` `0x14C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io8ctrl` `0x150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io9ctrl` `0x154` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io10ctrl` `0x158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io11ctrl` `0x15C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io12ctrl` `0x160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io13ctrl` `0x164` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io14ctrl` `0x168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io15ctrl` `0x16C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io16ctrl` `0x170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io17ctrl` `0x174` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io18ctrl` `0x178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io19ctrl` `0x17C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io20ctrl` `0x180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io21ctrl` `0x184` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io22ctrl` `0x188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io23ctrl` `0x18C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io24ctrl` `0x190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io25ctrl` `0x194` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io26ctrl` `0x198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io27ctrl` `0x19C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io28ctrl` `0x200` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io29ctrl` `0x204` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io30ctrl` `0x208` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io31ctrl` `0x20C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io32ctrl` `0x210` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io33ctrl` `0x214` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io34ctrl` `0x218` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io35ctrl` `0x21C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io36ctrl` `0x220` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io37ctrl` `0x224` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io38ctrl` `0x228` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io39ctrl` `0x22C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io40ctrl` `0x230` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io41ctrl` `0x234` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io42ctrl` `0x238` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io43ctrl` `0x23C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io44ctrl` `0x240` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io45ctrl` `0x244` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io46ctrl` `0x248` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`io47ctrl` `0x24C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`									`wkpull_up_dn` `RW 0x2`		`input_sel` `RW 0x2`		`ropdrain` `RW 0x0`	`rslewp` `RW 0x0`	`rslewn` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rpcdp` `RW 0x2C`								`rpcdn` `RW 0x38`
`pinmux_emac0_usefpga` `0x300` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_emac1_usefpga` `0x304` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_emac2_usefpga` `0x308` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_i2c0_usefpga` `0x30C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_i2c1_usefpga` `0x310` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_i2c_emac0_usefpga` `0x314` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_i2c_emac1_usefpga` `0x318` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_i2c_emac2_usefpga` `0x31C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_nand_usefpga` `0x320` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_spim0_usefpga` `0x328` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_spim1_usefpga` `0x32C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_spis0_usefpga` `0x330` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_spis1_usefpga` `0x334` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_uart0_usefpga` `0x338` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_uart1_usefpga` `0x33C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_mdio0_usefpga` `0x340` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_mdio1_usefpga` `0x344` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_mdio2_usefpga` `0x348` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_jtag_usefpga` `0x350` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`pinmux_sdmmc_usefpga` `0x354` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`hps_osc_clk` `0x358` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`reg` `RW 0x3F`
`io0_delay` `0x400` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io1_delay` `0x404` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io2_delay` `0x408` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io3_delay` `0x40C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io4_delay` `0x410` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io5_delay` `0x414` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io6_delay` `0x418` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io7_delay` `0x41C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io8_delay` `0x420` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io9_delay` `0x424` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io10_delay` `0x428` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io11_delay` `0x42C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io12_delay` `0x430` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io13_delay` `0x434` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io14_delay` `0x438` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io15_delay` `0x43C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io16_delay` `0x440` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io17_delay` `0x444` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io18_delay` `0x448` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io19_delay` `0x44C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io20_delay` `0x450` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io21_delay` `0x454` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io22_delay` `0x458` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io23_delay` `0x45C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io24_delay` `0x460` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io25_delay` `0x464` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io26_delay` `0x468` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io27_delay` `0x46C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io28_delay` `0x470` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io29_delay` `0x474` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io30_delay` `0x478` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io31_delay` `0x47C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io32_delay` `0x480` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io33_delay` `0x484` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io34_delay` `0x488` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io35_delay` `0x48C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io36_delay` `0x490` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io37_delay` `0x494` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io38_delay` `0x498` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io39_delay` `0x49C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io40_delay` `0x500` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io41_delay` `0x504` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io42_delay` `0x508` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io43_delay` `0x50C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io44_delay` `0x510` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io45_delay` `0x514` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io46_delay` `0x518` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`
`io47_delay` `0x51C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`output_val` `RW 0x0`					`Reserved`			`input_val` `RW 0x0`