pin4sel 

         HPS Pinmux Select for IO4
Module Instance Base Address Register Address
i_dedio_pinmux_csr 0xFFD13000 0xFFD13010

Size: 32

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

val

RW 0x9

pin4sel Fields

Bit Name Description Access Reset
3:0 val 
Select value determines which interface has been selected for IO4. It also determines the output_enable for the respective interface. Its value can range from 0 to 9.  
0000 (0) -- Pin connected to sdmmc.data2
0001 (1) -- Pin connected to usb0.data1
0010 (2) -- Pin connected to trace.d6
0011 (3) -- Pin connected to nand.wp_n
0100 (4) -- Pin connected to i2c0.sda
0101 (5) -- Pin connected to uart1.cts_n
0110 (6) -- reserved
0111 (7) -- Pin connected to spim0.clk
1000 (8) -- Pin connected to gpio0.io4  Note: Platform Designer also programs this encoding value if you select this pin as the clock manager external oscillator input.
1001 (9) -- reserved
 RW 0x9