pinmux_spis0_usefpga 

         Selection between HPS Pin and FPGA Interface for SPIS0 signals.  NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance Base Address Register Address
i_dedio_pinmux_csr 0xFFD13000 0xFFD13330

Size: 32

Offset: 0x330

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

sel

RW 0x0

pinmux_spis0_usefpga Fields

Bit Name Description Access Reset
0 sel 
Select connection for SPIS0.
Value Description
0 SPIS0 uses HPS IO Pins.
1 SPIS0 uses the FPGA Inteface.
RW 0x0