io30_delay

         Adds the delay chains in IO30
      
Module Instance Base Address Register Address
i_dedio_pinmux_csr 0xFFD13000 0xFFD13478

Size: 32

Offset: 0x478

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

output_val

RW 0x0

Reserved

input_val

RW 0x0

io30_delay Fields

Bit Name Description Access Reset
12:8 output_val
Depending on the value, it adds the chain delays in the output path of the Pinmux. The LSB serves as an enable.
Value Description
0 Intrinsic IO delay . This bypasses the delay chain and selects the data directly.
1 Intrinsic IO delay + Minimum Chain delay . Selects the data through the delay chain but no delay cell is enabled.
3 Intrinsic IO delay + Minimum+1Chain delay
5 Intrinsic IO delay + Minimum +2Chain delay
7 Intrinsic IO delay + Minimum +3Chain delay
9 Intrinsic IO delay + Minimum +4Chain delay
11 Intrinsic IO delay + Minimum+5 Chain delay
13 Intrinsic IO delay + Minimum +6Chain delay
15 Intrinsic IO delay + Minimum +7Chain delay
17 Intrinsic IO delay + Minimum +8Chain delay
19 Intrinsic IO delay + Minimum+9 Chain delay
21 Intrinsic IO delay + Minimum +10Chain delay
23 Intrinsic IO delay + Minimum+11 Chain delay
25 Intrinsic IO delay + Minimum +12Chain delay
27 Intrinsic IO delay + Minimum+13 Chain delay
29 Intrinsic IO delay + Minimum +14Chain delay
31 Intrinsic IO delay + Minimum +15Chain delay
RW 0x0
4:0 input_val
Depending on the value, it adds the chain delays in the input path of the Pinmux. The LSB serves as an enable.
Value Description
0 Intrinsic IO delay . This bypasses the delay chain and selects the data directly.
1 Intrinsic IO delay + Minimum Chain delay . Selects the data through the delay chain but no delay cell is enabled.
3 Intrinsic IO delay + Minimum+1Chain delay
5 Intrinsic IO delay + Minimum +2Chain delay
7 Intrinsic IO delay + Minimum +3Chain delay
9 Intrinsic IO delay + Minimum +4Chain delay
11 Intrinsic IO delay + Minimum+5 Chain delay
13 Intrinsic IO delay + Minimum +6Chain delay
15 Intrinsic IO delay + Minimum +7Chain delay
17 Intrinsic IO delay + Minimum +8Chain delay
19 Intrinsic IO delay + Minimum+9 Chain delay
21 Intrinsic IO delay + Minimum +10Chain delay
23 Intrinsic IO delay + Minimum+11 Chain delay
25 Intrinsic IO delay + Minimum +12Chain delay
27 Intrinsic IO delay + Minimum+13 Chain delay
29 Intrinsic IO delay + Minimum +14Chain delay
31 Intrinsic IO delay + Minimum +15Chain delay
RW 0x0