pin27sel 

         HPS Pinmux Select for IO3
Module Instance Base Address Register Address
i_dedio_pinmux_csr 0xFFD13000 0xFFD1306C

Size: 32

Offset: 0x6C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

val

RW 0x9

pin27sel Fields

Bit Name Description Access Reset
3:0 val 
Select value determines which interface has been selected for IO3. It also determines the output_enable for the respective interface. Its value can range from 0 to 9.  
0000 (0) -- Pin connected to emac1.rx_ctl
0001 (1) -- reserved
0010 (2) -- Pin connected to trace.d7
0011 (3) -- Pin connected to nand.re_n
0100 (4) -- Pin connected to i2c0.scl
0101 (5) -- Pin connected to uart0.rx
0110 (6) -- reserved
0111 (7) -- Pin connected to spim1.ss0_n
1000 (8) -- Pin connected to gpio1.io3  Note: Platform Designer also programs this encoding value if you select this pin as the clock manager external oscillator input.
1001 (9) -- reserved
 RW 0x9