pin29sel

         HPS Pinmux Select for IO5
      
Module Instance Base Address Register Address
i_dedio_pinmux_csr 0xFFD13000 0xFFD13074

Size: 32

Offset: 0x74

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

val

RW 0x9

pin29sel Fields

Bit Name Description Access Reset
3:0 val
Select value determines which interface has been selected for IO5. It also determines the output_enable for the respective interface. Its value can range from 0 to 9.  
0000 (0) -- Pin connected to emac1.txd1
0001 (1) -- reserved
0010 (2) -- Pin connected to trace.d5
0011 (3) -- Pin connected to nand.adq2
0100 (4) -- reserved
0101 (5) -- Pin connected to uart1.rts_n
0110 (6) -- Pin connected to spis1.mosi
0111 (7) -- reserved
1000 (8) -- Pin connected to gpio1.io5  Note: Platform Designer also programs this encoding value if you select this pin as the clock manager external oscillator input.
1001 (9) -- reserved
RW 0x9