rxftlr

This register controls the threshold value for the receive FIFO memory. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SPIENR register.

Module Instance	Base Address	Register Address
`spim0`	`0xFFF00000`	`0xFFF0001C`
`spim1`	`0xFFF01000`	`0xFFF0101C`

Offset: 0x1C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`rft` `RW 0x0`

rxftlr Fields

Bit	Name	Description	Access	Reset
7:0	`rft`	Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. When the number of receive FIFO entries is greater than or equal to this value + 1, the receive FIFO full interrupt is triggered.	`RW`	`0x0`