dr

This register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SPI_EN = 1. FIFOs are reset when SPI_EN = 0. The data register occupies thirty-six 32-bit locations in the address map (0x60 to 0xec). These are all aliases for the same data register. This is done to support burst accesses. .

Module Instance	Base Address	Register Address
`spim0`	`0xFFF00000`	`0xFFF00060 to 0xFFF000EC`
`spim1`	`0xFFF01000`	`0xFFF01060 to 0xFFF010EC`

Offset: 0x60 to 0xEC

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`dr` `RW 0x0`

dr Fields

Bit	Name	Description	Access	Reset
15:0	`dr`	When writing to this register, you must right-justify the data. Read data are automatically right-justified. Read = Receive FIFO buffer Write = Transmit FIFO buffer	`RW`	`0x0`