mwcr
This register controls the direction of the data word for the half-duplex Microwire serial protocol. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SPIENR register.
| Module Instance | Base Address | Register Address |
|---|---|---|
| spim0 | 0xFFF00000 | 0xFFF0000C |
| spim1 | 0xFFF01000 | 0xFFF0100C |
Offset: 0xC
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
mhs RW 0x0 |
mdd RW 0x0 |
mwmod RW 0x0 |
||||||||||||
mwcr Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 2 | mhs | Used to enable and disable the busy/ready handshaking interface for the Microwire protocol. When enabled, the SPI Master checks for a ready status from the target slave, after the transfer of the last data/control bit, before clearing the BUSY status in the SR register.
|
RW | 0x0 | ||||||
| 1 | mdd | Defines the direction of the data word when the Microwire serial protocol is used.
|
RW | 0x0 | ||||||
| 0 | mwmod | Defines whether the Microwire transfer is sequential or non-sequential. When sequential mode is used, only one control word is needed to transmit or receive a block of data words. When non-sequential mode is used, there must be a control word for each data word that is transmitted or received.
|
RW | 0x0 |