isr

This register reports the status of the SPI Master interrupts after they have been masked.

Module Instance	Base Address	Register Address
`spim0`	`0xFFF00000`	`0xFFF00030`
`spim1`	`0xFFF01000`	`0xFFF01030`

Offset: 0x30

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`										`mstis` `RO 0x0`	`rxfis` `RO 0x0`	`rxois` `RO 0x0`	`rxuis` `RO 0x0`	`txois` `RO 0x0`	`txeis` `RO 0x0`

isr Fields

Bit

Name

Description

Access

Reset

mstis

Multi-master contention status.

Value	Description
0x0	0 = ssi_mst_intr interrupt not active after masking
0x1	1 = ssi_mst_intr interrupt is active after masking

RO

0x0

rxfis

Full Status.

Value	Description
0x0	spi_rxf_intr interrupt is not active after masking
0x1	spi_rxf_intr interrupt is full after masking

RO

0x0

rxois

Overflow Status.

Value	Description
0x0	spi_rxo_intr interrupt is not active after masking
0x1	spi_rxo_intr interrupt is active after masking

RO

0x0

rxuis

Underflow Status.

Value	Description
0x0	spi_rxu_intr interrupt is not active after masking
0x1	spi_rxu_intr interrupt is active after masking

RO

0x0

txois

Overflow Status.

Value	Description
0x0	spi_txo_intr interrupt is not active after masking
0x1	spi_txo_intr interrupt is active after masking

RO

0x0

txeis

Empty status.

Value	Description
0x0	spi_txe_intr interrupt is not active after masking
0x1	spi_txe_intr interrupt is active after masking

RO

0x0