rxuicr
Receive FIFO Underflow Interrupt Clear Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| spim0 | 0xFFF00000 | 0xFFF00040 |
| spim1 | 0xFFF01000 | 0xFFF01040 |
Offset: 0x40
Access: RO
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
rxuicr RO 0x0 |
||||||||||||||
rxuicr Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 0 | rxuicr | This register reflects the status of the interrupt. A read from this register clears the spi_rxu_intr interrupt; writing has no effect. |
RO | 0x0 |