SPI Master Module Summary

Registers in the SPI Master module

Module Instance	Base Address
`spim0`	`0xFFF00000`
`spim1`	`0xFFF01000`

Register Address Offset	Bit Fields
`ctrlr0` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cfs` `RW 0x0`				`srl` `RW 0x0`	`Reserved`	`tmod` `RW 0x0`		`scpol` `RW 0x0`	`scph` `RW 0x0`	`frf` `RW 0x0`		`dfs` `RW 0x7`
`ctrlr1` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ndf` `RW 0x0`
`spienr` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`spi_en` `RW 0x0`
`mwcr` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`mhs` `RW 0x0`	`mdd` `RW 0x0`	`mwmod` `RW 0x0`
`ser` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`ser` `RW 0x0`
`baudr` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sckdv` `RW 0x0`
`txftlr` `0x18`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`tft` `RW 0x0`
`rxftlr` `0x1C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`rft` `RW 0x0`
`txflr` `0x20`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`txtfl` `RO 0x0`
`rxflr` `0x24`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`rxtfl` `RO 0x0`
`sr` `0x28`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`rff` `RO 0x0`	`rfne` `RO 0x0`	`tfe` `RO 0x1`	`tfnf` `RO 0x1`	`busy` `RO 0x0`
`imr` `0x2C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`rxfim` `RW 0x1`	`rxoim` `RW 0x1`	`rxuim` `RW 0x1`	`txoim` `RW 0x1`	`txeim` `RW 0x1`
`isr` `0x30`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`mstis` `RO 0x0`	`rxfis` `RO 0x0`	`rxois` `RO 0x0`	`rxuis` `RO 0x0`	`txois` `RO 0x0`	`txeis` `RO 0x0`
`risr` `0x34`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`rxfir` `RO 0x0`	`rxoir` `RO 0x0`	`rxuir` `RO 0x0`	`txoir` `RO 0x0`	`txeir` `RO 0x0`
`txoicr` `0x38`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`txoicr` `RO 0x0`
`rxoicr` `0x3C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`rxoicr` `RO 0x0`
`rxuicr` `0x40`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`rxuicr` `RO 0x0`
`icr` `0x48`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`icr` `RO 0x0`
`dmacr` `0x4C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`tdmae` `RW 0x0`	`rdmae` `RW 0x0`
`dmatdlr` `0x50`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`dmatdl` `RW 0x0`
`dmardlr` `0x54`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`dmardl` `RW 0x0`
`idr` `0x58`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`idr` `RO 0x5510000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`idr` `RO 0x5510000`
`spi_version_id` `0x5C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`spi_version_id` `RW 0x3332302A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`spi_version_id` `RW 0x3332302A`
`dr` `0x60`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`dr` `RW 0x0`
`rx_sample_dly` `0xFC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`									`rsd` `RW 0x0`