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1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions
5.4.1. Global Discovery Registers
5.4.2. Global Control Registers
5.4.3. Global Status Registers
5.4.4. Unit Discovery
5.4.5. Unit Control Registers
5.4.6. Unit Status Registers
PMON_USTS_L: PMON_UCADR +08h Size 32
PMON_USTS_H: PMON_UCADR +0Ch Size 32
5.4.7. Counter Control Registers
5.4.8. Data Registers
5.4.9. AXI4 Event Support
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5.4.6. Unit Status Registers
PMON_USTS_L: PMON_UCADR +08h Size 32
Field | Bit | Attribute | Default | Description |
---|---|---|---|---|
Cntr_Ov | 15:0 | R-W1C | 16’b0 | Counter Overflow If an overflow is detected from the corresponding data register, its overflow bit will be set.
Note: Write of ‘1’ will clear the bit.
|
Reserved | 32:16 | RV | 16’b0 | Reserved. |
PMON_USTS_H: PMON_UCADR +0Ch Size 32
Field | Bit | Attribute | Default | Description |
---|---|---|---|---|
Reserved | 32:0 | RV | 32’b0 | Reserved. |