Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817760
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions
1. About the Performance Monitor (PMON) FPGA IP x
1.1. Release Information
3. Performance Monitor IP Functional Description x
3.1. AXI4 Traffic Limitations
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP x
4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support
5. Performance Monitor (PMON) FPGA IP Interface Signals x
5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers
5.4. Registers x
5.4.1. Global Discovery Registers 5.4.2. Global Control Registers 5.4.3. Global Status Registers 5.4.4. Unit Discovery 5.4.5. Unit Control Registers PMON_UCTRL_L: PMON_UCADR Size 32 PMON_UCTRL_H PMON_UCADR +04h Size 32 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers 5.4.8. Data Registers 5.4.9. AXI4 Event Support
A. Performance Monitor (PMON) Library Functions x
A.1. Derived Parameters from PMON IP
1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions

5.4.5. Unit Control Registers

PMON_UCTRL_L: PMON_UCADR Size 32

Table 33.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
Freeze 0 RW-V 1’b0

Freeze.

If set to 1 the Counter Data registers in this unit block will be frozen.
Reserved 7:1 RV 7’b0 Reserved.
Rst_Ctrl 8 RW-V 1’b0

Reset Counter Control registers.

When set to 1, the Counter Control Registers in this unit block will be reset to 0.
Rst_Cntr 9 RW-V 1’b0

Reset Counter Data registers.

When set to 1, the Counter Data Registers in this unit block will be reset to 0. Will also reset any internal flags raised in unit monitor.
Reserved 31:10 RV 22'h0 Reserved.

PMON_UCTRL_H PMON_UCADR +04h Size 32

Table 34.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
Reserved 31:0 RV 32'h0 Reserved
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