1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions

1.1. Release Information

3.1. AXI4 Traffic Limitations

4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support

5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers

5.4.1. Global Discovery Registers 5.4.2. Global Control Registers 5.4.3. Global Status Registers PMON_GSTS_L: Offset: PMON_GCADR: GblStatAdr_offset Size 32 PMON_GSTS_H: Offset: PMON_GCADR: GblStatAdr_offset:0004h Size 32 5.4.4. Unit Discovery 5.4.5. Unit Control Registers 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers 5.4.8. Data Registers 5.4.9. AXI4 Event Support

A.1. Derived Parameters from PMON IP