External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Using the Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.1. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4
2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4 x
2.1.1.3.3.1. Guidelines for Selecting the LPDDR4 Component
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface 2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation For ModelSim* SE and Siemens* EDA QuestaSim*- Intel FPGA Edition Simulators For Synopsys VCS-MX and Cadence Xcelium
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

3.2.1. Running Simulation

To run a simulation, navigate to the simulation directory <example_design_directory>/sim/ed_sim/ and run the simulation script of your choice.

For ModelSim* SE and Siemens* EDA QuestaSim*- Intel FPGA Edition Simulators

  1. At the command prompt, change the working directory to: <example_design_directory>/sim/ed_sim/mentor.
  2. Invoke vsim by typing vsim, which launches a window where you can run the following commands.
  3. Run the following command in the transcript terminal:
    • source msim_setup.tcl
  4. Run the following command:
    • ld_debug
  5. When the command completes, add the desired signal to observe by right-clicking and selecting Add Wave.
    Figure 41. Select Add Wave
  6. To run the simulation, type this command:
    • run -all
  7. A successful simulation ends with the following message: Simulation stopped due to successful completion!

For Synopsys VCS-MX and Cadence Xcelium

The following are the steps to run simulation with the Synopsys VCS-MX simulator, however the steps are similar with Cadence Xcelium.

Working directory: <example_design_directory>/sim/ed_sim/synopsys/vcsmx

To run a simulation in non-interactive mode, follow these steps:

  1. On a single line, type: 
    sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\uniq_prior_final" USER_DEFINED_SIM_OPTIONS=""
  2. A successful simulation ends with the following message: Simulation stopped due to successful completion!

To run a simulation in interactive mode, follow these steps:

Note: If you have already generated a simv executable in noninteractive mode, delete the simv and simv.diadir file within the vcs folder.
  1. Open the vcs_setup.sh file and add a debug command:
    • vcs -debug_access+r
  2. Compile the design example by entering the following command:
    • sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="- xlrm\ uniq_prior_final" SKIP_SIM=1
  3. To start the simulation in interactive mode, type the following command in the console:
    • simv -gui&
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